參數(shù)資料
型號: CY7C43646AV
廠商: Cypress Semiconductor Corp.
英文描述: 3.3V 1K 4K 16K x 36 x 18 x 2 Tri Bus FIFO
中文描述: 3.3每1000 4K的16K的× 36 × 18 × 2三總線先進(jìn)先出
文件頁數(shù): 26/40頁
文件大小: 644K
代理商: CY7C43646AV
CY7C43646AV
CY7C43666AV
CY7C43686AV
Document #: 38-06026 Rev. *C
Page 26 of 40
Notes:
40. If Port B size is word or byte, ORB is set LOW by the last word or byte Read from FIFO2, respectively.
41. t
is the minimum time between a rising CLKA edge and a rising CLKB edge for ORB to transition HIGH and to clock the next word to the FIFO1 output
register in three CLKB cycles. If the time between the rising CLKA edge and rising CLKB edge is less than t
SKEW1
, then the transition of ORB HIGH and load
of the first word to the output register may occur one CLKB cycle later than shown.
Switching Waveforms
(continued)
t
CLKH
t
CLKL
t
ENS
t
CLK
t
ENH
t
ENS
t
ENH
t
A
t
DS
W1
LOW
t
DH
HIGH
HIGH
FIFO1 Empty
LOW
LOW
Old Data in FIFO1 Output Register
W1
t
ENS
t
ENH
t
REF
t
REF
t
CLKH
t
CLKL
t
CLK
t
SKEW1
[41]
CLKA
CSA
W/RA
MBA
ENA
FFA/IRA
A
0
35
CLKB
EFB/ORB
CSB
MBB
RENB
B
0
17
ORB Flag Timing and First Data Word Fall Through when FIFO1 is Empty (FWFT Mode)
[40]
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