- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379094 > CY7C43644AV (Cypress Semiconductor Corp.) 3.3V 1Kx36 x2 Bidirectional Synchronous FIFO w/ Bus Matching(3.3V 1K x36 x2 雙向同步先進(jìn)先出帶總線匹配) PDF資料下載
參數(shù)資料
| 型號(hào)： | CY7C43644AV |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 3.3V 1Kx36 x2 Bidirectional Synchronous FIFO w/ Bus Matching(3.3V 1K x36 x2 雙向同步先進(jìn)先出帶總線匹配) |
| 中文描述： | 3.3 1Kx36 x2雙向同步FIFO瓦特/總線匹配（3.3每1000 x36 x2雙向同步先進(jìn)先出帶總線匹配） |
| 文件頁(yè)數(shù)： | 7/38頁(yè) |
| 文件大小： | 581K |
| 代理商： | CY7C43644AV |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)當(dāng)前第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)
CY7C43644AV
CY7C43664AV/CY7C43684AV
7
PRELIMINARY
AC Test Loads and Waveforms (-10 & -15)
AC Test Loads and Waveforms (-7)
Switching Characteristics
Over the Operating Range
Parameter
Description
CY7C43644/
64/84AV
–
7
Min.
CY7C43644/
64/84AV
–
10
Min.
CY7C43644/
64/84AV
–
15
Min.
Unit
Max.
Max.
Max.
f
S
t
CLK
t
CLKH
t
CLKL
t
DS
Clock Frequency, CLKA or CLKB
133
100
67
MHz
Clock Cycle Time, CLKA or CLKB
7.5
10
15
ns
Pulse Duration, CLKA or CLKB HIGH
3.5
4
6
ns
Pulse Duration, CLKA or CLKB LOW
Set-Up Time, A
0
–
35
before CLKA
↑
and B
0
–
35
before
CLKB
↑
Set-Up Time, CSA, W/RA, ENA, and MBA before
CLKA
↑
; CSB, W/RB, ENB, and MBB before CLKB
↑
Set-Up Time, MRS1, MRS2, PRS1, or PRS2 LOW
before CLKA
↑
or CLKB
↑
[7]
Set-Up Time, FS0 and FS1 before MRS1 and MRS2
HIGH
3.5
4
6
ns
3
4
5
ns
t
ENS
3
4
5
ns
t
RSTS
2.5
4
5
ns
t
FSS
5
7
7.5
ns
t
BES
Set-Up Time, BE/FWFT before MRS1 and MRS2
HIGH
5
7
7.5
ns
t
SPMS
t
SDS
t
SENS
t
FWS
t
DH
Set-Up Time, SPM before MRS1 and MRS2 HIGH
Set-Up Time, FS0/SD before CLKA
↑
Set-Up Time, FS1/SEN before CLKA
↑
Set-Up Time, BE/FWFT before CLKA
↑
Hold Time, A
0
–
35
after CLKA
↑
and B
0
–
35
after
CLKB
↑
Hold Time, CSA, W/RA, ENA, and MBA after
CLKA
↑
; CSB, W/RB, ENB, and MBB after CLKB
↑
5
7
7.5
ns
3
4
5
ns
3
4
5
ns
0
0
0
ns
0
0
0
ns
t
ENH
1
2
0
ns
Note:
7.
Requirement to count the clock edge as one of at least four needed to reset a FIFO.
3.0V
3.3V
OUTPUT
R2=680
C
L
=30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
≤
3 ns
≤
3 ns
ALL INPUT PULSES
R1=330
3.0V
GND
90%
10%
90%
10%
≤
3 ns
≤
3 ns
ALL INPUT PULSES
I/O
50
V
CC
/2
Z0=50
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C43684AV | 3.3V 16K x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching(3.3V 16K x36 x2 雙向同步先進(jìn)先出帶總線匹配) |
| CY7C43666AV | 3.3V 4K x36/x18x2 Tri Bus FIFO(3.3V 4K x36/x18x2 三路總線先進(jìn)先出) |
| CY7C43686AV | 3.3V 16K x36/x18x2 Tri Bus FIFO(3.3V 16K x36/x18x2 三路總線先進(jìn)先出) |
| CY7C453 | 2Kx9 Cascadable Clocked FIFOs with Programmable Flags(帶可編程標(biāo)記的2Kx9可級(jí)聯(lián)定時(shí)的先進(jìn)先出) |
| CY7C451 | 512x9 Cascadable Clocked FIFOs with Programmable Flags(帶可編程標(biāo)記的512x9可級(jí)聯(lián)定時(shí)的先進(jìn)先出) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C43644AV-10AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Bi-Dir 1K x 36 x 2 128-Pin TQFP |
| CY7C43663-15AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C43664-7AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C43682-15AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C43683-10AI | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。