參數(shù)資料
型號: CY7C43644AV
廠商: Cypress Semiconductor Corp.
英文描述: 3.3V 1Kx36 x2 Bidirectional Synchronous FIFO w/ Bus Matching(3.3V 1K x36 x2 雙向同步先進(jìn)先出帶總線匹配)
中文描述: 3.3 1Kx36 x2雙向同步FIFO瓦特/總線匹配(3.3每1000 x36 x2雙向同步先進(jìn)先出帶總線匹配)
文件頁數(shù): 23/38頁
文件大?。?/td> 581K
代理商: CY7C43644AV
CY7C43644AV
CY7C43664AV/CY7C43684AV
23
PRELIMINARY
Notes:
35. If Port B size is word or byte, FFB is set LOW by the last word or byte write of the long-word, respectively.
36. t
is the minimum time between a rising CLKA edge and a rising CLKB edge for FFB to transition HIGH in the next CLKB cycle. If the time between the
rising CLKA edge and rising CLKB edge is less than t
SKEW1
, then the transition of FFB HIGH may occur one CLKB cycle later than shown.
Switching Waveforms
(continued)
t
CLKH
t
CLKL
t
ENS
t
ENH
t
A
LOW
LOW
HIGH
FIFO2 Full
LOW
LOW
t
ENS
t
ENH
t
WFF
t
WFF
t
CLKH
t
CLKL
t
CLK
t
CLK
t
SKEW1[36]
t
DH
t
DS
t
ENH
t
ENS
Previous Word in FIFO12 Output Register
Next Word From FIFO2
To FIFO2
LOW
CLKA
CSA
W/RA
MBA
ENA
EFA/ORA
A
0
35
CLKB
FFB/IRB
CSB
W/RB
MBB
ENB
B
0
35
FFB Flag Timing and First Available Write when FIFO2 is Full (CY Standard Mode)
[35]
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