參數(shù)資料
型號(hào): CY7C43644AV
廠商: Cypress Semiconductor Corp.
英文描述: 3.3V 1Kx36 x2 Bidirectional Synchronous FIFO w/ Bus Matching(3.3V 1K x36 x2 雙向同步先進(jìn)先出帶總線匹配)
中文描述: 3.3 1Kx36 x2雙向同步FIFO瓦特/總線匹配(3.3每1000 x36 x2雙向同步先進(jìn)先出帶總線匹配)
文件頁數(shù): 16/38頁
文件大小: 581K
代理商: CY7C43644AV
CY7C43644AV
CY7C43664AV/CY7C43684AV
16
PRELIMINARY
Notes:
25. If Port B size is word or byte, EFB is set LOW by the last word or byte read from FIFO1, respectively.
26. t
is the minimum time between a rising CLKA edge and a rising CLKB edge for ORB to transition HIGH and to clock the next word to the FIFO1 output
register in three CLKB cycles. If the time between the rising CLKA edge and rising CLKB edge is less than t
SKEW1
, then the transition of ORB HIGH and
load of the first word to the output register may occur one CLKB cycle later than shown.
Switching Waveforms
(continued)
t
CLKH
t
CLKL
t
ENS
t
CLK
t
EN
t
ENS
t
EN
t
A
t
DS
W1
LOW
t
DH
HIGH
HIGH
FIFO1 Empty
LOW
HIGH
LOW
Old Data in FIFO1 Output Register
W1
t
ENS
t
ENH
t
REF
t
REF
t
CLKH
t
CLKL
t
CLK
t
SKEW[26]
CLKA
CSA
W/RA
MBA
ENA
FFA/IRA
A
0
35
CLKB
EFB/ORB
CSB
W/RB
MBB
ENB
B
0
35
ORB Flag Timing and First Data Word Fall Through when FIFO1 is Empty (FWFT Mode)
[25]
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