參數(shù)資料
型號: CY7C1475V25
廠商: Cypress Semiconductor Corp.
英文描述: 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture(帶NoBL結(jié)構(gòu)的72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM)
中文描述: 72兆位(2米x 36/4M x 18/1M × 72)流體系結(jié)構(gòu),通過與總線延遲(帶總線延遲結(jié)構(gòu)的72兆位通過的SRAM(2米x 36/4M x 18/1M × 72)流的SRAM)
文件頁數(shù): 26/32頁
文件大小: 1134K
代理商: CY7C1475V25
CY7C1471V25
CY7C1473V25
CY7C1475V25
Document #: 38-05287 Rev. *I
Page 26 of 32
Figure 3
shows ZZ Mode timing waveform.
[23, 24]
Figure 3. ZZ
Mode Timing
Switching Waveforms
(continued)
tZZ
I
SUPPLY
CLK
ZZ
tZZREC
ALL INPUTS
(except ZZ)
DON’T CARE
IDDZZ
tZZI
tRZZI
Outputs (Q)
High-Z
DESELECT or READ Only
Notes
23.Device must be deselected when entering ZZ mode. See
“Truth Table” on page 11
for all possible signal conditions to deselect the device.
24.DQs are in high-Z when exiting ZZ sleep mode.
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CY7C1473V25 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture(帶NoBL結(jié)構(gòu)的72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM)
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