參數(shù)資料
型號： CY7C1475V25
廠商： Cypress Semiconductor Corp.
英文描述： 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture(帶NoBL結(jié)構(gòu)的72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM)
中文描述： 72兆位（2米x 36/4M x 18/1M × 72）流體系結(jié)構(gòu)，通過與總線延遲（帶總線延遲結(jié)構(gòu)的72兆位通過的SRAM（2米x 36/4M x 18/1M × 72）流的SRAM）
文件頁數(shù)： 23/32頁
文件大小： 1134K
代理商： CY7C1475V25
CY7C1471V25
CY7C1473V25
CY7C1475V25
Document #: 38-05287 Rev. *I
Page 23 of 32
Switching Characteristics
Over the Operating Range. Timing reference level is 1.25V when V
DDQ
= 2.5V and is 0.9V when V
DDQ
= 1.8V. Test conditions
shown in (a) of
“AC Test Loads and Waveforms” on page 22
unless otherwise noted.
Parameter
Description
133 MHz
100 MHz
Unit
Min
Max
Min
Max
t
POWER
Clock
1
1
ms
t
CYC
t
CH
t
CL
Output Times
Clock Cycle Time
7.5
10
ns
Clock HIGH
2.5
3.0
ns
Clock LOW
2.5
3.0
ns
t
CDV
t
DOH
t
CLZ
t
CHZ
t
OEV
t
OELZ
t
OEHZ
Setup Times
Data Output Valid After CLK Rise
6.5
8.5
ns
Data Output Hold After CLK Rise
Clock to Low-Z
[16, 17, 18]
Clock to High-Z
[16, 17, 18]
2.5
2.5
ns
3.0
3.0
ns
3.8
4.5
ns
OE LOW to Output Valid
OE LOW to Output Low-Z
[16, 17, 18]
OE HIGH to Output High-Z
[16, 17, 18]
3.0
3.8
ns
0
0
ns
3.0
4.0
ns
t
AS
t
ALS
t
WES
t
CENS
t
DS
t
CES
Hold Times
Address Setup Before CLK Rise
1.5
1.5
ns
ADV/LD Setup Before CLK Rise
1.5
1.5
ns
WE, BW
X
Setup Before CLK Rise
CEN Setup Before CLK Rise
Data Input Setup Before CLK Rise
1.5
1.5
ns
1.5
1.5
ns
1.5
1.5
ns
Chip Enable Setup Before CLK Rise
1.5
1.5
ns
t
AH
t
ALH
t
WEH
t
CENH
t
DH
t
CEH
Address Hold After CLK Rise
0.5
0.5
ns
ADV/LD Hold After CLK Rise
0.5
0.5
ns
WE, BW
X
Hold After CLK Rise
CEN Hold After CLK Rise
0.5
0.5
ns
0.5
0.5
ns
Data Input Hold After CLK Rise
0.5
0.5
ns
Chip Enable Hold After CLK Rise
0.5
0.5
ns
Notes
15.This part has a voltage regulator internally; t
POWER
is the time that the power needs to be supplied above V
DD
(minimum) initially, before a read or write operation
can be initiated.
16.t
, t
,t
, and t
are specified with AC test conditions shown in part (b) of
“AC Test Loads and Waveforms” on page 22
. Transition is measured ±200 mV
from steady-state voltage.
17.At any supplied voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z before Low-Z under the same system conditions.
18.This parameter is sampled and not 100% tested.
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