參數(shù)資料
型號: CY7C1475V25
廠商: Cypress Semiconductor Corp.
英文描述: 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture(帶NoBL結構的72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM)
中文描述: 72兆位(2米x 36/4M x 18/1M × 72)流體系結構,通過與總線延遲(帶總線延遲結構的72兆位通過的SRAM(2米x 36/4M x 18/1M × 72)流的SRAM)
文件頁數(shù): 24/32頁
文件大?。?/td> 1134K
代理商: CY7C1475V25
CY7C1471V25
CY7C1473V25
CY7C1475V25
Document #: 38-05287 Rev. *I
Page 24 of 32
Switching Waveforms
Figure 1
shows read-write timing waveform.
[19, 20, 21]
Figure 1. Read/Write Timing
WRITE
D(A1)
1
2
3
4
5
6
7
8
9
CLK
tCYC
tCL
tCH
10
CE
tCEH
tCES
WE
CEN
tCENH
tCENS
BW
X
ADV/LD
tAH
tAS
ADDRESS
A1
A2
A3
A4
A5
A6
A7
tDH
tDS
DQ
COMMAND
tCLZ
D(A1)
D(A2)
Q(A4)
Q(A3)
D(A2+1)
tDOH
tCHZ
tCDV
WRITE
D(A2)
BURST
WRITE
D(A2+1)
READ
Q(A3)
READ
Q(A4)
BURST
READ
Q(A4+1)
WRITE
D(A5)
READ
Q(A6)
WRITE
D(A7)
DESELECT
OE
tOEV
tOELZ
tOEHZ
DON’T CARE
UNDEFINED
D(A5)
tDOH
Q(A4+1)
D(A7)
Q(A6)
Notes
19.For this waveform ZZ is tied LOW.
20.When CE is LOW, CE
is LOW, CE
is HIGH, and CE
is LOW. When CE is HIGH, CE
is HIGH, CE
is LOW or CE
is HIGH.
21.Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.
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CY7C1473V25 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture(帶NoBL結構的72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM)
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CY7C1471V33 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture(帶NoBL結構的72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM)
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