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參數(shù)資料
| 型號： | CY7C1475V25 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture(帶NoBL結(jié)構(gòu)的72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM) |
| 中文描述： | 72兆位（2米x 36/4M x 18/1M × 72）流體系結(jié)構(gòu)，通過與總線延遲（帶總線延遲結(jié)構(gòu)的72兆位通過的SRAM（2米x 36/4M x 18/1M × 72）流的SRAM） |
| 文件頁數(shù)： | 22/32頁 |
| 文件大?。?/td> | 1134K |
| 代理商： | CY7C1475V25 |
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CY7C1471V25
CY7C1473V25
CY7C1475V25
Document #: 38-05287 Rev. *I
Page 22 of 32
Capacitance
Tested initially and after any design or process change that may affect these parameters.
Parameter
Description
Test Conditions
100 TQFP
Max.
165 FBGA
Max.
209 FBGA
Max.
Unit
C
ADDRESS
C
DATA
C
CTRL
C
CLK
C
IO
Address Input Capacitance
T
A
= 25
°
C, f = 1 MHz,
V
DD
= 2.5V
V
DDQ
= 2.5V
6
6
6
pF
Data Input Capacitance
5
5
5
pF
Control Input Capacitance
8
8
8
pF
Clock Input Capacitance
6
6
6
pF
Input-Output Capacitance
5
5
5
pF
Thermal Resistance
Tested initially and after any design or process change that may affect these parameters.
Parameter
Description
Test Conditions
100 TQFP
Package
165 FBGA
Package
209 FBGA
Package
Unit
Θ
JA
Thermal Resistance
(Junction to Ambient)
Test conditions follow
standard test methods
and procedures for
measuring thermal
impedance, according to
EIA/JESD51.
24.63
16.3
15.2
°
C/W
Θ
JC
Thermal Resistance
(Junction to Case)
2.28
2.1
1.7
°
C/W
AC Test Loads and Waveforms
OUTPUT
R = 1667
R = 1538
5 pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
OUTPUT
R
L
= 50
Z
0
= 50
V
L
= 1.25V
2.5V
ALL INPUT PULSES
V
DDQ
GND
90%
10%
90%
10%
≤
1 ns
≤
1 ns
(c)
2.5V IO Test Load
OUTPUT
R = 14 K
R = 14 K
5 pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
OUTPUT
R
L
= 50
Z
0
= 50
V
L
= 0.9V
1.8V
ALL INPUT PULSES
V
DDQ
– 0.2
0.2
90%
10%
90%
10%
≤
1 ns
≤
1 ns
(c)
1.8V IO Test Load
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1473V25 | 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture(帶NoBL結(jié)構(gòu)的72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM) |
| CY7C1475V33 | 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture(帶NoBL結(jié)構(gòu)的72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM) |
| CY7C1471V33 | 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture(帶NoBL結(jié)構(gòu)的72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM) |
| CY7C1482V25-200BZXC | 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1475V33-100AXC | 制造商:Cypress Semiconductor 功能描述:72MB (1MBX72) NOBL FLOW-THRU, 3.3V CORE, 2.5/3.3V I/O - Bulk |
| CY7C1475V33-100BGC | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC SGL 3.3V 72MBIT 1MX72 8.5NS 209FBGA - Bulk |
| CY7C1475V33-133BGC | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC OCTAL 3.3V 72MBIT 1MX72 6.5NS 209FBGA - Bulk |
| CY7C14802BC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C14802XC | 制造商:Cypress Semiconductor 功能描述: |
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