參數(shù)資料
型號： CY7C1475V33
廠商： Cypress Semiconductor Corp.
英文描述： 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture(帶NoBL結構的72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM)
中文描述： 72兆位（2米x 36/4M x 18/1M × 72）流體系結構，通過與總線延遲（帶總線延遲結構的72兆位通過的SRAM（2米x 36/4M x 18/1M × 72）流的SRAM）
文件頁數(shù)： 1/32頁
文件大小： 1138K
代理商： CY7C1475V33
72-Mbit (2M x 36/4M x 18/1M x 72)
Flow-Through SRAM with NoBL Architecture
CY7C1471V33
CY7C1473V33
CY7C1475V33
Cypress Semiconductor Corporation
Document #: 38-05288 Rev. *J
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised July 04, 2007
Features
No Bus Latency (NoBL) architecture eliminates dead
cycles between write and read cycles
Supports up to 133 MHz bus operations with zero wait states
Data is transferred on every clock
Pin compatible and functionally equivalent to ZBT devices
Internally self timed output buffer control to eliminate the
need to use OE
Registered inputs for flow through operation
Byte Write capability
3.3V/2.5V IO supply (V
DDQ
)
Fast clock-to-output times
— 6.5 ns (for 133-MHz device)
Clock Enable (CEN) pin to enable clock and suspend
operation
Synchronous self timed writes
Asynchronous Output Enable (OE)
CY7C1471V33, CY7C1473V33 available in
JEDEC-standard Pb-free 100-Pin TQFP, Pb-free and
non-Pb-free 165-Ball FBGA package. CY7C1475V33
available in Pb-free and non-Pb-free 209-Ball FBGA
package
Three Chip Enables (CE
1
, CE
2
, CE
3
) for simple depth
expansion
Automatic power down feature available using ZZ mode or
CE deselect
IEEE 1149.1 JTAG Boundary Scan compatible
Burst Capability — linear or interleaved burst order
Low standby power
Functional Description
[1]
The CY7C1471V33, CY7C1473V33 and CY7C1475V33 are
3.3V, 2M x 36/4M x 18/1M x 72 synchronous flow through burst
SRAMs designed specifically to support unlimited true
back-to-back read or write operations without the insertion of
wait states. The CY7C1471V33, CY7C1473V33 and
CY7C1475V33 are equipped with the advanced No Bus
Latency (NoBL) logic required to enable consecutive read or
write operations with data being transferred on every clock
cycle. This feature dramatically improves the throughput of
data through the SRAM, especially in systems that require
frequent write-read transitions.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. The clock input is qualified by
the Clock Enable (CEN) signal, which when deasserted
suspends operation and extends the previous clock
cycle.Maximum access delay from the clock rise is 6.5 ns
(133-MHz device).
Write operations are controlled by two or four Byte Write Select
(BW
X
) and a Write Enable (WE) input. All writes are conducted
with on-chip synchronous self timed write circuitry.
Three synchronous Chip Enables (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. To avoid bus contention,
the output drivers are synchronously tri-stated during the data
portion of a write sequence.
Selection Guide
133 MHz
6.5
305
120
117 MHz
8.5
275
120
Unit
ns
mA
mA
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Note
AN1064, SRAM System Guidelines
相關PDF資料
PDF描述
CY7C1471V33 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture(帶NoBL結構的72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM)
CY7C1482V25-200BZXC 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
CY7C1480V25-200BZC 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
CY7C1480V25-200BZI 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
CY7C1480V25-200BZXC 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
相關代理商/技術參數(shù)
參數(shù)描述
CY7C1475V33-100AXC 制造商:Cypress Semiconductor 功能描述:72MB (1MBX72) NOBL FLOW-THRU, 3.3V CORE, 2.5/3.3V I/O - Bulk
CY7C1475V33-100BGC 制造商:Cypress Semiconductor 功能描述:SRAM SYNC SGL 3.3V 72MBIT 1MX72 8.5NS 209FBGA - Bulk
CY7C1475V33-133BGC 制造商:Cypress Semiconductor 功能描述:SRAM SYNC OCTAL 3.3V 72MBIT 1MX72 6.5NS 209FBGA - Bulk
CY7C14802BC 制造商:Cypress Semiconductor 功能描述:
CY7C14802XC 制造商:Cypress Semiconductor 功能描述:
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