參數(shù)資料
型號(hào)： CY7C1475V33
廠商： Cypress Semiconductor Corp.
英文描述： 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture(帶NoBL結(jié)構(gòu)的72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM)
中文描述： 72兆位（2米x 36/4M x 18/1M × 72）流體系結(jié)構(gòu)，通過(guò)與總線延遲（帶總線延遲結(jié)構(gòu)的72兆位通過(guò)的SRAM（2米x 36/4M x 18/1M × 72）流的SRAM）
文件頁(yè)數(shù)： 31/32頁(yè)
文件大小： 1138K
代理商： CY7C1475V33
CY7C1471V33
CY7C1473V33
CY7C1475V33
Document #: 38-05288 Rev. *J
Page 31 of 32
Document History Page
Document Title: CY7C1471V33/CY7C1473V33/CY7C1475V33, 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM
with NoBL Architecture
Document Number: 38-05288
Issue
Date
**
114675
08/06/02
PKS
New Data Sheet
*A
121521
02/07/03
CJM
Updated features for package offering
Updated ordering information
Changed Advanced Information to Preliminary
*B
223721
See ECN
NJY
Changed timing diagrams
Changed logic block diagrams
Modified Functional Description
Modified “Functional Overview” section
Added boundary scan order for all packages
Included thermal numbers and capacitance values for all packages
Removed 150-MHz speed grade offering
Included ISB and IDD values
Changed package outline for 165FBGA package and 209-Ball BGA package
Removed 119-BGA package offering
*C
235012
See ECN
RYQ
Minor Change: The data sheets do not match on the spec system and
external web
*D
243572
See ECN
NJY
Changed ball H2 from V
DD
to NC in the 165-Ball FBGA package in page 6
Modified capacitance values on page 21
*E
299511
See ECN
SYT
Removed 117-MHz Speed Bin
Changed
Θ
JA
from 16.8 to 24.63
°
C/W and
Θ
JC
from 3.3 to 2.28
°
C/W for 100
TQFP Package on Page # 21
Added Pb-free information for 100-Pin TQFP, 165 FBGA and 209 BGA
Packages
Added comment of ‘Pb-free BG packages availability’ below the Ordering
Information
*F
320197
See ECN
PCI
Corrected part number typos in the logic block diagram on page# 2
*G
331513
See ECN
PCI
Address expansion pins/balls in the pinouts for all packages are modified as
per JEDEC standard
Added Address Expansion pins in the Pin Definitions Table
Added Industrial Operating Range
Modified V
OL
, V
OH
Test Conditions
Updated Ordering Information Table
*H
416221
See ECN
RXU
Converted from Preliminary to Final
Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Removed 100MHz Speed bin & Added 117MHz Speed bin
Changed the description of I
X
from Input Load Current to Input Leakage
Current on page# 19
Changed the I
X
current values of MODE on page # 19 from –5
μ
A and 30
μ
A
to –30
μ
A and 5
μ
A
Changed the I
X
current values of ZZ on page # 19 from –30
μ
A and 5
μ
A
to –5
μ
A and 30
μ
A
Changed V
IH
< V
DD
to V
IH
< V
DD
on page # 19
Replaced Package Name column with Package Diagram in the Ordering
Information table
Updated the Ordering Information Table
REV.
ECN NO.
Orig. of Change
Description of Change
相關(guān)PDF資料
PDF描述
CY7C1471V33 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture(帶NoBL結(jié)構(gòu)的72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM)
CY7C1482V25-200BZXC 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
CY7C1480V25-200BZC 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
CY7C1480V25-200BZI 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
CY7C1480V25-200BZXC 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY7C1475V33-100AXC 制造商:Cypress Semiconductor 功能描述:72MB (1MBX72) NOBL FLOW-THRU, 3.3V CORE, 2.5/3.3V I/O - Bulk
CY7C1475V33-100BGC 制造商:Cypress Semiconductor 功能描述:SRAM SYNC SGL 3.3V 72MBIT 1MX72 8.5NS 209FBGA - Bulk
CY7C1475V33-133BGC 制造商:Cypress Semiconductor 功能描述:SRAM SYNC OCTAL 3.3V 72MBIT 1MX72 6.5NS 209FBGA - Bulk
CY7C14802BC 制造商:Cypress Semiconductor 功能描述:
CY7C14802XC 制造商:Cypress Semiconductor 功能描述:
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