參數(shù)資料
型號： CY7C1475V33
廠商： Cypress Semiconductor Corp.
英文描述： 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture(帶NoBL結構的72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM)
中文描述： 72兆位（2米x 36/4M x 18/1M × 72）流體系結構，通過與總線延遲（帶總線延遲結構的72兆位通過的SRAM（2米x 36/4M x 18/1M × 72）流的SRAM）
文件頁數(shù)： 17/32頁
文件大?。?/td> 1138K
代理商： CY7C1475V33
CY7C1471V33
CY7C1473V33
CY7C1475V33
Document #: 38-05288 Rev. *J
Page 17 of 32
3.3V TAP AC Test Conditions
Input pulse levels................................................ V
SS
to 3.3V
Input rise and fall times................................................... 1 ns
Input timing reference levels...........................................1.5V
Output reference levels...................................................1.5V
Test load termination supply voltage...............................1.5V
2.5V TAP AC Test Conditions
Input pulse levels.................................................V
SS
to 2.5V
Input rise and fall time .....................................................1 ns
Input timing reference levels.........................................1.25V
Output reference levels ................................................1.25V
Test load termination supply voltage ............................1.25V
3.3V TAP AC Output Load Equivalent
TDO
1.5V
20pF
Z = 50
50
2.5V TAP AC Output Load Equivalent
TDO
1.25V
20pF
Z = 50
50
TAP DC Electrical Characteristics And Operating Conditions
(0°C < T
A
< +70°C; V
DD
= 3.3V ±0.165V unless otherwise noted)
[12]
Parameter
Description
V
OH1
Output HIGH Voltage
Test Conditions
Min
2.4
2.0
2.9
2.1
Max
Unit
V
V
V
V
V
V
V
V
V
V
V
V
μA
I
OH
= –4.0 mA, V
DDQ
= 3.3V
I
OH
= –1.0 mA, V
DDQ
= 2.5V
I
OH
= –100 μA
V
OH2
Output HIGH Voltage
V
DDQ
= 3.3V
V
DDQ
= 2.5V
V
DDQ
= 3.3V
V
DDQ
= 2.5V
V
DDQ
= 3.3V
V
DDQ
= 2.5V
V
DDQ
= 3.3V
V
DDQ
= 2.5V
V
DDQ
= 3.3V
V
DDQ
= 2.5V
V
OL1
Output LOW Voltage
I
OL
= 8.0 mA
I
OL
= 1.0 mA
I
OL
= 100 μA
0.4
0.4
0.2
0.2
V
OL2
Output LOW Voltage
V
IH
Input HIGH Voltage
2.0
1.7
–0.3
–0.3
–5
V
DD
+ 0.3
V
DD
+ 0.3
0.8
0.7
5
V
IL
Input LOW Voltage
I
X
Input Load Current
GND < V
IN
< V
DDQ
Note
12.All voltages refer to V
SS
(GND).
相關PDF資料
PDF描述
CY7C1471V33 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture(帶NoBL結構的72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM)
CY7C1482V25-200BZXC 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
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相關代理商/技術參數(shù)
參數(shù)描述
CY7C1475V33-100AXC 制造商:Cypress Semiconductor 功能描述:72MB (1MBX72) NOBL FLOW-THRU, 3.3V CORE, 2.5/3.3V I/O - Bulk
CY7C1475V33-100BGC 制造商:Cypress Semiconductor 功能描述:SRAM SYNC SGL 3.3V 72MBIT 1MX72 8.5NS 209FBGA - Bulk
CY7C1475V33-133BGC 制造商:Cypress Semiconductor 功能描述:SRAM SYNC OCTAL 3.3V 72MBIT 1MX72 6.5NS 209FBGA - Bulk
CY7C14802BC 制造商:Cypress Semiconductor 功能描述:
CY7C14802XC 制造商:Cypress Semiconductor 功能描述:
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