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參數(shù)資料
| 型號(hào)： | CY7C1475V33 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture(帶NoBL結(jié)構(gòu)的72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM) |
| 中文描述： | 72兆位（2米x 36/4M x 18/1M × 72）流體系結(jié)構(gòu)，通過與總線延遲（帶總線延遲結(jié)構(gòu)的72兆位通過的SRAM（2米x 36/4M x 18/1M × 72）流的SRAM） |
| 文件頁數(shù)： | 11/32頁 |
| 文件大?。?/td> | 1138K |
| 代理商： | CY7C1475V33 |
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CY7C1471V33
CY7C1473V33
CY7C1475V33
Document #: 38-05288 Rev. *J
Page 11 of 32
Truth Table
The truth table for CY7C1471V33, CY7C1473V33, CY7C1475V33 follows.
[2, 3, 4, 5, 6, 7, 8]
Operation
Address
Used
None
None
None
None
External
CE
1
CE
2
CE
3
ZZ
ADV/LD
WE
BW
X
OE
CEN
CLK
DQ
Deselect Cycle
Deselect Cycle
Deselect Cycle
Continue Deselect Cycle
Read Cycle
(Begin Burst)
Read Cycle
(Continue Burst)
NOP/Dummy Read
(Begin Burst)
Dummy Read
(Continue Burst)
Write Cycle
(Begin Burst)
Write Cycle
(Continue Burst)
NOP/Write Abort
(Begin Burst)
Write Abort
(Continue Burst)
Ignore Clock Edge (Stall)
Sleep Mode
H
X
X
X
L
X
X
L
X
H
X
H
X
X
L
L
L
L
L
L
L
L
L
H
L
X
X
X
X
H
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L->H
L->H
L->H
L->H
L->H Data Out (Q)
Tri-State
Tri-State
Tri-State
Tri-State
Next
X
X
X
L
H
X
X
L
L
L->H Data Out (Q)
External
L
H
L
L
L
H
X
H
L
L->H
Tri-State
Next
X
X
X
L
H
X
X
H
L
L->H
Tri-State
External
L
H
L
L
L
L
L
X
L
L->H
Data In (D)
Next
X
X
X
L
H
X
L
X
L
L->H
Data In (D)
None
L
H
L
L
L
L
H
X
L
L->H
Tri-State
Next
X
X
X
L
H
X
H
X
L
L->H
Tri-State
Current
None
X
X
X
X
X
X
L
H
X
X
X
X
X
X
X
X
H
X
L->H
X
-
Tri-State
Notes
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. BW
= L signifies at least one Byte Write Select is active, BW
X
= Valid signifies that the desired Byte Write
Selects are asserted, see
“Truth Table for Read/Write” on page 12
for details.
3. Write is defined by BW
, and WE. See
“Truth Table for Read/Write” on page 12
.
4. When a Write cycle is detected, all IOs are tri-stated, even during Byte Writes.
5. The DQs and DQP
pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. CEN = H, inserts wait states.
7. Device powers up deselected with the IOs in a tri-state condition, regardless of OE.
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP
X
= tri-state when OE
is inactive or when the device is deselected, and DQs and DQP
X
= data when OE is active.
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PDF描述 |
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| CY7C1471V33 | 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture(帶NoBL結(jié)構(gòu)的72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM) |
| CY7C1482V25-200BZXC | 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM |
| CY7C1480V25-200BZC | 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM |
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| CY7C1480V25-200BZXC | 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1475V33-100AXC | 制造商:Cypress Semiconductor 功能描述:72MB (1MBX72) NOBL FLOW-THRU, 3.3V CORE, 2.5/3.3V I/O - Bulk |
| CY7C1475V33-100BGC | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC SGL 3.3V 72MBIT 1MX72 8.5NS 209FBGA - Bulk |
| CY7C1475V33-133BGC | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC OCTAL 3.3V 72MBIT 1MX72 6.5NS 209FBGA - Bulk |
| CY7C14802BC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C14802XC | 制造商:Cypress Semiconductor 功能描述: |
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