- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379077 > CY7C1474V33-250BGI (CYPRESS SEMICONDUCTOR CORP) 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL⑩ Architecture PDF資料下載
參數(shù)資料
| 型號： | CY7C1474V33-250BGI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL⑩ Architecture |
| 中文描述： | 1M X 72 ZBT SRAM, 3 ns, PBGA209 |
| 封裝： | 14 X 22 MM, 1.76 MM HEIGHT, FBGA-209 |
| 文件頁數(shù)： | 9/29頁 |
| 文件大小： | 471K |
| 代理商： | CY7C1474V33-250BGI |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁當(dāng)前第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁
CY7C1470V33
CY7C1472V33
CY7C1474V33
Document #: 38-05289 Rev. *I
Page 9 of 29
Notes:
1. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip Enables active. BWx = 0 signifies at least one Byte Write Select is active, BWx = Valid
signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.
2. Write is defined by WE and BW
. See Write Cycle Description table for details.
3. When a Write cycle is detected, all I/Os are tri-stated, even during Byte Writes.
4. The DQ and DQP pins are controlled by the current cycle and the OE signal.
5. CEN = H inserts wait states.
6. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle DQ
s
and DQP
[a:d]
= tri-state when OE
is inactive or when the device is deselected, and DQ
s
= data when OE is active.
Truth Table
[1, 2, 3, 4, 5, 6, 7]
Operation
Address Used
CE
ZZ
ADV/LD
WE
BW
x
X
OE
CEN
CLK
DQ
Deselect Cycle
None
H
L
L
X
X
L
L-H
Tri-State
Continue
Deselect Cycle
None
X
L
H
X
X
X
L
L-H
Tri-State
Read Cycle
(Begin Burst)
External
L
L
L
H
X
L
L
L-H
Data Out (Q)
Read Cycle
(Continue Burst)
Next
X
L
H
X
X
L
L
L-H
Data Out (Q)
NOP/Dummy Read
(Begin Burst)
External
L
L
L
H
X
H
L
L-H
Tri-State
Dummy Read
(Continue Burst)
Next
X
L
H
X
X
H
L
L-H
Tri-State
Write Cycle
(Begin Burst)
External
L
L
L
L
L
X
L
L-H
Data In (D)
Write Cycle
(Continue Burst)
Next
X
L
H
X
L
X
L
L-H
Data In (D)
NOP/Write Abort
(Begin Burst)
None
L
L
L
L
H
X
L
L-H
Tri-State
Write Abort
(Continue Burst)
Next
X
L
H
X
H
X
L
L-H
Tri-State
Ignore Clock Edge
(Stall)
Current
X
L
X
X
X
X
H
L-H
-
Sleep Mode
None
X
H
X
X
X
X
X
X
Tri-State
[+] Feedback
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1474V33-250BGXI | 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL⑩ Architecture |
| CY7C1475V25-100BGI | 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL⑩ Architecture |
| CY7C1475V25-100BGXI | 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL⑩ Architecture |
| CY7C1475V25-133BGI | 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL⑩ Architecture |
| CY7C1475V25-133BGXI | 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL⑩ Architecture |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1475BV25-133BGXI | 功能描述:靜態(tài)隨機存取存儲器 72MB (1Mx72) 2.5v 133MHz FLO-THRU 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1475V33-100AXC | 制造商:Cypress Semiconductor 功能描述:72MB (1MBX72) NOBL FLOW-THRU, 3.3V CORE, 2.5/3.3V I/O - Bulk |
| CY7C1475V33-100BGC | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC SGL 3.3V 72MBIT 1MX72 8.5NS 209FBGA - Bulk |
| CY7C1475V33-133BGC | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC OCTAL 3.3V 72MBIT 1MX72 6.5NS 209FBGA - Bulk |
| CY7C14802BC | 制造商:Cypress Semiconductor 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。