參數(shù)資料
型號: CY7C1474V33-250BGI
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL⑩ Architecture
中文描述: 1M X 72 ZBT SRAM, 3 ns, PBGA209
封裝: 14 X 22 MM, 1.76 MM HEIGHT, FBGA-209
文件頁數(shù): 29/29頁
文件大?。?/td> 471K
代理商: CY7C1474V33-250BGI
CY7C1470V33
CY7C1472V33
CY7C1474V33
Document #: 38-05289 Rev. *I
Page 29 of 29
*H
416221
See ECN
RXU
Converted from Preliminary to Final
Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Changed Three-state to Tri-state
Changed the description of I
X
from Input Load Current to Input Leakage
Current on page# 18
Changed the I
X
current values of MODE on page # 18 from –5
μ
A and 30
μ
A
to –30
μ
A and 5
μ
A
Changed the I
X
current values of ZZ on page # 18 from –30
μ
A and 5
μ
A
to –5
μ
A and 30
μ
A
Changed V
DDQ
<
VDD
to V
DDQ
< V
DD
in page #18
Replaced Package Name column with Package Diagram in the Ordering
Information table
Updated the Ordering Information Table
Corrected the typo in the pin configuration for 209-Ball FBGA pinout
(Corrected the ball name for H9 to V
SS
from V
SSQ
).
Added the Maximum Rating for Supply Voltage on V
DDQ
Relative to GND.
Changed t
TH
, t
TL
from 25 ns to 20 ns and t
TDOV
from 5 ns to 10 ns in TAP
AC Switching Characteristics table.
Updated the Ordering Information table.
*I
472335
See ECN
VKN
Document Title: CY7C1470V33/CY7C1472V33/CY7C1474V33 72-Mbit (2M x 36/4M x 18/1M x 72)
Pipelined SRAM with NoBL Architecture
Document Number: 38-05289
Orig. of
Change
REV.
ECN No.
Issue Date
Description of Change
[+] Feedback
相關(guān)PDF資料
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