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參數(shù)資料
| 型號(hào)： | CY7C1474V33-250BGI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL⑩ Architecture |
| 中文描述： | 1M X 72 ZBT SRAM, 3 ns, PBGA209 |
| 封裝： | 14 X 22 MM, 1.76 MM HEIGHT, FBGA-209 |
| 文件頁(yè)數(shù)： | 8/29頁(yè) |
| 文件大小： | 471K |
| 代理商： | CY7C1474V33-250BGI |
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CY7C1470V33
CY7C1472V33
CY7C1474V33
Document #: 38-05289 Rev. *I
Page 8 of 29
On the next clock rise the data presented to DQ
and DQP
(DQ
a,b,c,d,e,f,g,h
/DQP
a,b,c,d,e,f,g,h
DQ
a,b,c,d
/DQP
a,b,c,d
for CY7C1470V33 & DQ
a,b
/DQP
a,b
for
CY7C1472V33) (or a subset for byte write operations, see
Write Cycle Description table for details) inputs is latched into
the device and the write is complete.
The data written during the Write operation is controlled by BW
(BW
a,b,c,d,e,f,g,h
for
CY7C1474V33,
CY7C1470V33 and BW
a,b
for CY7C1472V33) signals. The
CY7C1470V33, CY7C1472V33, and CY7C1474V33 provides
Byte Write capability that is described in the Write Cycle
Description table. Asserting the Write Enable input (WE) with
the selected Byte Write Select (BW) input will selectively write
to only the desired bytes. Bytes not selected during a Byte
Write operation will remain unaltered. A synchronous
self-timed Write mechanism has been provided to simplify the
Write operations. Byte Write capability has been included in
order to greatly simplify Read/Modify/Write sequences, which
can be reduced to simple Byte Write operations.
Because
the
CY7C1470V33,
CY7C1474V33 are common I/O devices, data should not be
driven into the device while the outputs are active. The Output
Enable (OE) can be deasserted HIGH before presenting data
to the DQ
and DQP (DQ
a,b,c,d,e,f,g,h
/DQP
a,b,c,d,e,f,g,h
for
CY7C1474V33, DQ
a,b,c,d
/DQP
a,b,c,d
for CY7C1470V33 and
DQ
a,b
/DQP
a,b
for CY7C1472V33) inputs. Doing so will tri-state
the output drivers. As a safety precaution, DQ
and DQP
(DQ
a,b,c,d,e,f,g,h
/DQP
a,b,c,d,e,f,g,h
DQ
a,b,c,d
/DQP
a,b,c,d
for CY7C1470V33 and DQ
a,b
/DQP
a,b
for
CY7C1472V33) are automatically tri-stated during the data
portion of a Write cycle, regardless of the state of OE.
for
CY7C1474V33,
BW
a,b,c,d
for
CY7C1472V33,
and
for
CY7C1474V33,
Burst Write Accesses
The CY7C1470V33, CY7C1472V33, and CY7C1474V33 has
an on-chip burst counter that allows the user the ability to
supply a single address and conduct up to four Write opera-
tions without reasserting the address inputs. ADV/LD must be
driven LOW in order to load the initial address, as described
in the Single Write Access section above. When ADV/LD is
driven HIGH on the subsequent clock rise, the Chip Enables
(CE
1
, CE
2
, and CE
3
) and WE inputs are ignored and the burst
counter is incremented. The correct BW (BW
a,b,c,d,e,f,g,h
for
ZZ Mode Electrical Characteristics
CY7C1474V33, BW
a,b,c,d
for CY7C1470V33 and BW
a,b
for
CY7C1472V33) inputs must be driven in each cycle of the
burst write in order to write the correct bytes of data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE
1
, CE
2
, and CE
3
, must remain inactive
for the duration of t
ZZREC
after the ZZ input returns LOW.
Interleaved Burst Address Table
(MODE = Floating or V
DD
)
First
Address
Address
A1,A0
A1,A0
00
01
01
00
10
11
11
10
Second
Third
Address
A1,A0
10
11
00
01
Fourth
Address
A1,A0
11
10
01
00
Linear Burst Address Table (MODE = GND)
First
Address
A1,A0
00
01
10
11
Second
Address
A1,A0
01
10
11
00
Third
Address
A1,A0
10
11
00
01
Fourth
Address
A1,A0
11
00
01
10
Parameter
I
DDZZ
t
ZZS
t
ZZREC
t
ZZI
t
RZZI
Description
Test Conditions
Min.
Max
120
2t
CYC
Unit
mA
ns
ns
ns
ns
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ active to sleep current
ZZ Inactive to exit sleep current
ZZ
>
V
DD
0.2V
ZZ
>
V
DD
0.2V
ZZ
<
0.2V
This parameter is sampled
This parameter is sampled
2t
CYC
2t
CYC
0
[+] Feedback
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| CY7C1475V25-133BGXI | 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL⑩ Architecture |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1475BV25-133BGXI | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 72MB (1Mx72) 2.5v 133MHz FLO-THRU 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1475V33-100AXC | 制造商:Cypress Semiconductor 功能描述:72MB (1MBX72) NOBL FLOW-THRU, 3.3V CORE, 2.5/3.3V I/O - Bulk |
| CY7C1475V33-100BGC | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC SGL 3.3V 72MBIT 1MX72 8.5NS 209FBGA - Bulk |
| CY7C1475V33-133BGC | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC OCTAL 3.3V 72MBIT 1MX72 6.5NS 209FBGA - Bulk |
| CY7C14802BC | 制造商:Cypress Semiconductor 功能描述: |
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