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參數(shù)資料
| 型號： | CY7C1474V33-250BGI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL⑩ Architecture |
| 中文描述： | 1M X 72 ZBT SRAM, 3 ns, PBGA209 |
| 封裝： | 14 X 22 MM, 1.76 MM HEIGHT, FBGA-209 |
| 文件頁數(shù)： | 6/29頁 |
| 文件大?。?/td> | 471K |
| 代理商： | CY7C1474V33-250BGI |
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CY7C1470V33
CY7C1472V33
CY7C1474V33
Document #: 38-05289 Rev. *I
Page 6 of 29
Pin Definitions
Pin Name
A0
A1
A
BW
a
BW
b
BW
c
BW
d
BW
e
BW
f
BW
g
BW
h
WE
I/O Type
Input-
Synchronous
Pin Description
Address Inputs used to select one of the address locations
. Sampled at the rising edge of
the CLK.
Input-
Synchronous
Byte Write Select Inputs, active LOW
. Qualified with WE to conduct writes to the SRAM.
Sampled on the rising edge of CLK. BW
a
controls DQ
a
and DQP
a
, BW
b
controls DQ
b
and DQP
b
,
BW
c
controls DQ
c
and DQP
c
, BW
d
controls DQ
d
and DQP
d
, BW
e
controls DQ
e
and DQP
e
, BW
f
controls DQ
f
and DQP
f
, BW
g
controls DQ
g
and DQP
g
, BW
h
controls DQ
h
and DQP
h
.
Input-
Synchronous
Input-
Synchronous
Write Enable Input, active LOW
. Sampled on the rising edge of CLK if CEN is active LOW. This
signal must be asserted LOW to initiate a write sequence.
Advance/Load Input used to advance the on-chip address counter or load a new address
.
When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a
new address can be loaded into the device for an access. After being deselected, ADV/LD should
be driven LOW in order to load a new address.
Clock Input
. Used to capture all synchronous inputs to the device. CLK is qualified with CEN.
CLK is only recognized if CEN is active LOW.
Chip Enable 1 Input, active LOW
. Sampled on the rising edge of CLK. Used in conjunction with
CE
2
and CE
3
to select/deselect the device.
Chip Enable 2 Input, active HIGH
. Sampled on the rising edge of CLK. Used in conjunction with
CE
1
and CE
3
to select/deselect the device.
Chip Enable 3 Input, active LOW
. Sampled on the rising edge of CLK. Used in conjunction with
CE
1
and
CE
2
to select/deselect the device.
Output Enable, active LOW
. Combined with the synchronous logic block inside the device to
control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs.
When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during
the data portion of a write sequence, during the first clock when emerging from a deselected state
and when the device has been deselected.
Clock Enable Input, active LOW
. When asserted LOW the clock signal is recognized by the
SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN does not
deselect the device, CEN can be used to extend the previous cycle when required.
Bidirectional Data I/O lines
. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by A
[17:0]
during the previous clock rise of the read cycle. The direction of the pins is
controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave
as outputs. When HIGH, DQ
a
–DQ
d
are placed in a tri-state condition. The outputs are automat-
ically tri-stated during the data portion of a write sequence, during the first clock when emerging
from a deselected state, and when the device is deselected, regardless of the state of OE.
Bidirectional Data Parity I/O lines
. Functionally, these signals are identical to DQ
X
. During write
sequences, DQP
a
is controlled by BW
a
, DQP
b
is controlled by BW
b
, DQP
c
is controlled by BW
c
,
and DQP
d
is controlled by BW
d
, DQP
e
is controlled by BW
e
, DQP
f
is controlled by BW
f
, DQP
g
is controlled by BW
g
, DQP
h
is controlled by BW
h
.
Mode Input
. Selects the burst order of the device. Tied HIGH selects the interleaved burst order.
Pulled LOW selects the linear burst order. MODE should not change states during operation.
When left floating MODE will default HIGH, to an interleaved burst order.
Serial data-out to the JTAG circuit
. Delivers data on the negative edge of TCK.
ADV/LD
CLK
Input-
Clock
Input-
CE
1
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Asynchronous
CE
2
CE
3
OE
CEN
Input-
Synchronous
DQ
S
I/O-
Synchronous
DQP
X
I/O-
Synchronous
MODE
Input Strap Pin
TDO
JTAG Serial
Output
Synchronous
JTAG Serial Input
Synchronous
TDI
Serial data-In to the JTAG circuit
. Sampled on the rising edge of TCK.
[+] Feedback
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1474V33-250BGXI | 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL⑩ Architecture |
| CY7C1475V25-100BGI | 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL⑩ Architecture |
| CY7C1475V25-100BGXI | 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL⑩ Architecture |
| CY7C1475V25-133BGI | 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL⑩ Architecture |
| CY7C1475V25-133BGXI | 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL⑩ Architecture |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1475BV25-133BGXI | 功能描述:靜態(tài)隨機存取存儲器 72MB (1Mx72) 2.5v 133MHz FLO-THRU 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1475V33-100AXC | 制造商:Cypress Semiconductor 功能描述:72MB (1MBX72) NOBL FLOW-THRU, 3.3V CORE, 2.5/3.3V I/O - Bulk |
| CY7C1475V33-100BGC | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC SGL 3.3V 72MBIT 1MX72 8.5NS 209FBGA - Bulk |
| CY7C1475V33-133BGC | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC OCTAL 3.3V 72MBIT 1MX72 6.5NS 209FBGA - Bulk |
| CY7C14802BC | 制造商:Cypress Semiconductor 功能描述: |
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