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參數(shù)資料
| 型號(hào)： | CY7C1464AV25 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL Architecture(帶NoBL結(jié)構(gòu)的36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM) |
| 中文描述： | 36兆位（1米x 36/2M x 18/512K × 72）流水線的SRAM架構(gòu)的總線延遲（帶總線延遲結(jié)構(gòu)的36兆位（1米x 36/2M x 18/512K × 72）流水線的SRAM） |
| 文件頁(yè)數(shù)： | 8/27頁(yè) |
| 文件大小： | 465K |
| 代理商： | CY7C1464AV25 |
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CY7C1460AV25
CY7C1462AV25
CY7C1464AV25
Document #: 38-05354 Rev. *D
Page 8 of 27
CY7C1460AV25, BW
a,b,c,d
for CY7C1460AV25 and BW
a,b
for
CY7C1462AV25) inputs must be driven in each cycle of the
burst write in order to write the correct bytes of data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE
1
, CE
2
, and CE
3
, must remain inactive
for the duration of t
ZZREC
after the ZZ input returns LOW.
Truth Table
[1, 2, 3, 4, 5, 6, 7]
Interleaved Burst Address Table
(MODE = Floating or V
DD
)
First
Address
Address
A1,A0
00
01
10
11
Second
Third
Address
A1,A0
10
11
00
01
Fourth
Address
A1,A0
11
10
01
00
A1,A0
01
00
11
10
Linear Burst Address Table (MODE = GND)
First
Address
A1,A0
00
01
10
11
Second
Address
A1,A0
01
10
11
00
Third
Address
A1,A0
10
11
00
01
Fourth
Address
A1,A0
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
I
DDZZ
t
ZZS
t
ZZREC
t
ZZI
t
RZZI
Description
Test Conditions
Min.
Max.
100
2t
CYC
Unit
mA
ns
ns
ns
ns
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ active to sleep current
ZZ Inactive to exit sleep current
ZZ
>
V
DD
0.2V
ZZ
>
V
DD
0.2V
ZZ
<
0.2V
This parameter is sampled
This parameter is sampled
2t
CYC
2t
CYC
0
Operation
Address
Used
None
None
External
Next
External
Next
External
Next
None
Next
Current
None
CE
H
X
L
X
L
X
L
X
X
X
X
ZZ
L
L
L
L
L
L
L
L
L
L
L
H
ADV/LD
L
H
L
H
L
H
L
H
L
H
X
X
WE
X
X
H
X
H
X
L
X
L
X
X
X
BW
x
X
X
X
X
X
X
L
L
H
H
X
X
OE CEN CLK
X
L
X
L
L
L
L
L
H
L
H
L
X
L
X
L
X
L
X
L
X
H
X
X
DQ
Deselect Cycle
Continue Deselect Cycle
Read Cycle (Begin Burst)
Read Cycle (Continue Burst)
NOP/Dummy Read (Begin Burst)
Dummy Read (Continue Burst)
Write Cycle (Begin Burst)
Write Cycle (Continue Burst)
NOP/WRITE ABORT (Begin Burst)
WRITE ABORT (Continue Burst)
IGNORE CLOCK EDGE (Stall)
Sleep MODE
L-H
L-H
L-H Data Out (Q)
L-H Data Out (Q)
L-H
Tri-State
L-H
Tri-State
L-H
Data In (D)
L-H
Data In (D)
L-H
Tri-State
L-H
Tri-State
L-H
X
Tri-State
Tri-State
Tri-State
–
Notes:
1. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip Enables active. BWx = L signifies at least one Byte Write Select is active, BWx = Valid
signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.
2. Write is defined by WE and BW
. See Write Cycle Description table for details.
3. When a write cycle is detected, all I/Os are tri-stated, even during byte writes.
4. The DQ and DQP pins are controlled by the current cycle and the OE signal.
5. CEN = H inserts wait states.
6. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles.During a read cycle DQ
s
and DQP
X
= Three-state when
OE is inactive or when the device is deselected, and DQ
s
=data when OE is active.
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