參數(shù)資料
型號(hào)： CY7C1464AV25
廠商： Cypress Semiconductor Corp.
英文描述： 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL Architecture(帶NoBL結(jié)構(gòu)的36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM)
中文描述： 36兆位（1米x 36/2M x 18/512K × 72）流水線的SRAM架構(gòu)的總線延遲（帶總線延遲結(jié)構(gòu)的36兆位（1米x 36/2M x 18/512K × 72）流水線的SRAM）
文件頁(yè)數(shù)： 20/27頁(yè)
文件大小： 465K
代理商： CY7C1464AV25
CY7C1460AV25
CY7C1462AV25
CY7C1464AV25
Document #: 38-05354 Rev. *D
Page 20 of 27
Switching Waveforms
Read/Write/Timing
[23, 24, 25]
NOP, STALL and DESELECT Cycles
[23, 24, 26]
Notes:
23.For this waveform ZZ is tied low.
24.When CE is LOW, CE
is LOW, CE
is HIGH and CE
is LOW. When CE is HIGH,CE
is HIGH or CE
is LOW or CE
is HIGH.
25.Order of the Burst sequence is determined by the status of the MODE (0=Linear, 1=Interleaved).Burst operations are optional.
26.The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle.
WRITE
D(A1)
1
2
3
4
5
6
7
8
9
CLK
tCYC
t
CL
t
CH
10
CE
t
CEH
t
CES
WE
CEN
t
CENH
t
CENS
BW
x
ADV/LD
t
AH
t
AS
ADDRESS
A1
A2
A3
A4
A5
A6
A7
t
DH
t
DS
Data
In-Out (DQ)
t
CLZ
D(A1)
D(A2)
D(A5)
Q(A4)
Q(A3)
D(A2+1)
t
DOH
t
CHZ
t
CO
WRITE
D(A2)
BURST
WRITE
D(A2+1)
READ
Q(A3)
READ
Q(A4)
BURST
READ
Q(A4+1)
WRITE
D(A5)
READ
Q(A6)
WRITE
D(A7)
DESELECT
OE
t
OEV
t
OELZ
t
OEHZ
t
DOH
DON’T CARE
UNDEFINED
Q(A6)
Q(A4+1)
READ
Q(A3)
4
5
6
7
8
9
10
CLK
CE
WE
CEN
BWx
ADV/LD
ADDRESS
A3
A4
A5
D(A4)
Data
In-Out (DQ)
A1
Q(A5)
WRITE
D(A4)
STALL
WRITE
D(A1)
1
2
3
READ
Q(A2)
STALL
NOP
READ
Q(A5)
DESELECT
CONTINUE
DESELECT
DON’T CARE
UNDEFINED
t
CHZ
A2
D(A1)
Q(A2)
Q(A3)
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CY7C1462AV25 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL Architecture(帶NoBL結(jié)構(gòu)的36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM)
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CY7C1464AV33 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL Architecture(帶NoBL結(jié)構(gòu)的36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM)
CY7C1462AV33 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL Architecture(帶NoBL結(jié)構(gòu)的36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY7C1464AV25-167BGC 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 512kx72 36M NoBL PL 靜態(tài)隨機(jī)存取存儲(chǔ)器 COM RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C1464AV25-167BGCES 制造商:Cypress Semiconductor 功能描述:36MB NOBL 512KB X 72 PIPELINE 2.5V - Bulk
CY7C1464AV25-200BGC 制造商:Cypress Semiconductor 功能描述:SRAM SYNC OCTAL 2.5V 36MBIT 512KX72 3.2NS 209FBGA - Bulk
CY7C1464AV33-167BGI 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 512Kx72 3.3V NoBL PL 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C146-55JC 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Dual 5V 16K-Bit 2K x 8 55ns 52-Pin PLCC 制造商:Cypress Semiconductor 功能描述:2K X 8 DUAL-PORT SRAM, 55 ns, PQCC52
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