- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379075 > CY7C1464AV25 (Cypress Semiconductor Corp.) 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL Architecture(帶NoBL結(jié)構(gòu)的36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM) PDF資料下載
參數(shù)資料
| 型號： | CY7C1464AV25 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL Architecture(帶NoBL結(jié)構(gòu)的36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM) |
| 中文描述： | 36兆位（1米x 36/2M x 18/512K × 72）流水線的SRAM架構(gòu)的總線延遲（帶總線延遲結(jié)構(gòu)的36兆位（1米x 36/2M x 18/512K × 72）流水線的SRAM） |
| 文件頁數(shù)： | 27/27頁 |
| 文件大?。?/td> | 465K |
| 代理商： | CY7C1464AV25 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁當前第27頁
CY7C1460AV25
CY7C1462AV25
CY7C1464AV25
Document #: 38-05354 Rev. *D
Page 27 of 27
Document History Page
Document Title: CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 36-Mbit (1-Mbit x 36/2-Mbit x 18/512K x 72) Pipelined
SRAM with NoBL Architecture
Document Number: 38-05354
Orig. of
Change
**
254911
See ECN
SYT
New data sheet
Part number changed from previous revision (new and old part number
differ by the letter “A”)
*A
303533
See ECN
SYT
Changed H9 pin from V
SSQ
to V
SS
on the Pin Configuration table for 209
FBGA on Page # 5
Changed the test condition from V
DD
= Min. to V
DD
= Max for V
OL
in the
Electrical Characteristics table
Replaced
Θ
JA
and
Θ
JC
from TBD to respective Thermal Values for All
Packages on the Thermal Resistance Table
Changed I
DD
from 450, 400 & 350 mA to 435, 385 & 335 mA for 250, 200
and 167 Mhz respectively
Changed I
SB1
from 190, 180 and 170 mA to 185 mA for 250, 200 and 167
Mhz respectively
Changed I
SB2
from 80 mA to 100 mA for all frequencies
Changed I
SB3
from 180, 170 & 160 mA to 160 mA for 250, 200 and 167
Mhz respectively
Changed I
SB4
from 100 mA to 110 mA for all frequencies
Changed C
IN
, C
CLK
and C
I/O
to 6.5, 3 and 5.5 pF from 5, 5 and 7 pF for
TQFP Package
Changed t
CO
from 3.0 to 3.2 ns and t
DOH
from 1.3 ns to 1.5 ns for 200 Mhz
Speed Bin
Added lead-free information for 100 TQFP, 165 FBGA and 209 FBGA
packages
*B
331778
See ECN
SYT
Modified Address Expansion balls in the pinouts for 165 FBGA and 209
FBGA Package as per JEDEC standards and updated the Pin Definitions
accordingly
Modified V
OL,
V
OH
test conditions
Changed C
IN
, C
CLK
and C
I/O
to 7, 7and 6 pF from 5, 5 and 7 pF for 165
FBGA Package
Added Industrial Temperature Grade
Changed I
SB2
and I
SB4
from 100 and 110 mA to 120 and 135 mA respec-
tively
Updated the Ordering Information by Shading and Unshading MPNs as per
availability
*C
417547
See ECN
RXU
Converted from Preliminary to Final
Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Modified test condition from V
DDQ
< V
DD
to
V
DDQ
≤
V
DD
Changed I
X
current value in MODE from –5 & 30
μ
A to –30 & 5
μ
A respec-
tively and also Changed I
X
current value in ZZ from –30 & 5
μ
A to –5 & 30
μ
A respectively on page# 19
Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in
the Electrical Characteristics Table
Replaced Package Name column with Package Diagram in the Ordering
Information table
Replaced Package Diagram of 51-85050 from *A to *B
*D
473650
See ECN
VKN
Added the Maximum Rating for Supply Voltage on V
DDQ
Relative to GND.
Changed t
TH
, t
TL
from 25 ns to 20 ns and t
TDOV
from 5 ns to 10 ns in TAP
AC Switching Characteristics table.
Updated the Ordering Information table.
REV.
ECN No.
Issue Date
Description of Change
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1462AV25 | 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL Architecture(帶NoBL結(jié)構(gòu)的36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM) |
| CY7C1460AV33 | 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL Architecture(帶NoBL結(jié)構(gòu)的36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM) |
| CY7C1464AV33 | 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL Architecture(帶NoBL結(jié)構(gòu)的36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM) |
| CY7C1462AV33 | 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL Architecture(帶NoBL結(jié)構(gòu)的36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM) |
| CY7C1472V33-167AXI | 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1464AV25-167BGC | 功能描述:靜態(tài)隨機存取存儲器 512kx72 36M NoBL PL 靜態(tài)隨機存取存儲器 COM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1464AV25-167BGCES | 制造商:Cypress Semiconductor 功能描述:36MB NOBL 512KB X 72 PIPELINE 2.5V - Bulk |
| CY7C1464AV25-200BGC | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC OCTAL 2.5V 36MBIT 512KX72 3.2NS 209FBGA - Bulk |
| CY7C1464AV33-167BGI | 功能描述:靜態(tài)隨機存取存儲器 512Kx72 3.3V NoBL PL 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C146-55JC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Dual 5V 16K-Bit 2K x 8 55ns 52-Pin PLCC 制造商:Cypress Semiconductor 功能描述:2K X 8 DUAL-PORT SRAM, 55 ns, PQCC52 |
發(fā)布緊急采購，3分鐘左右您將得到回復。