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參數(shù)資料
| 型號(hào)： | CY7C1361C-117BGC |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM |
| 中文描述： | 9兆位（256 × 36/512K × 18）流通過(guò)的SRAM |
| 文件頁(yè)數(shù)： | 21/30頁(yè) |
| 文件大?。?/td> | 491K |
| 代理商： | CY7C1361C-117BGC |
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PRELIMINARY
CY7C1361C
CY7C1363C
Document #: 38-05541 Rev. *A
Page 21 of 30
t
OEHZ
Set-up Times
t
AS
t
ADS
t
ADVS
t
WES
OE HIGH to Output High-Z
[17, 18, 19]
3.5
3.5
3.5
ns
Address Set-up Before CLK Rise
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
ns
ns
ADSP, ADSC Set-up Before CLK Rise
ADV Set-up Before CLK Rise
GW, BWE, BW
[A:D]
Set-up Before CLK
Rise
Data Input Set-up Before CLK Rise
Chip Enable Set-up
t
DS
t
CES
Hold Times
t
AH
t
ADH
t
WEH
t
ADVH
t
DH
t
CEH
Notes:
16.This part has a voltage regulator internally; t
POWER
is the time that the power needs to be supplied above V
DD
( minimum) initially, before a read or write operation
can be initiated.
17.t
, t
,t
, and t
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
18.At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions
19.This parameter is sampled and not 100% tested.
20.Timing reference level is 1.5V when V
= 3.3V and is 1.25V when V
DDQ
= 2.5V.
21.Test conditions shown in (a) of AC Test Loads unless otherwise noted.
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
Address Hold After CLK Rise
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
ADSP, ADSC Hold After CLK Rise
GW,BWE, BW
[A:D]
Hold After CLK Rise
ADV Hold After CLK Rise
Data Input Hold After CLK Rise
Chip Enable Hold After CLK Rise
Switching Characteristics
Over the Operating Range
[20, 21]
Parameter
Description
133 MHz
Min.
117 MHz
Min.
100 MHz
Min.
Unit
Max.
Max.
Max.
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| CY7C1361C-133AJXC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 256Kx36 3.3V COM Sync FT 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1361C-133AJXCKJ | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1361C-133AJXCT | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 256Kx36 3.3V COM Sync FT 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1361C-133AXC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 256Kx36 3.3V COM Sync FT 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1361C-133AXCKJ | 制造商:Cypress Semiconductor 功能描述: |
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