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參數(shù)資料
| 型號： | CY7C1361C-117BGC |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM |
| 中文描述： | 9兆位（256 × 36/512K × 18）流通過的SRAM |
| 文件頁數(shù)： | 14/30頁 |
| 文件大?。?/td> | 491K |
| 代理商： | CY7C1361C-117BGC |
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PRELIMINARY
CY7C1361C
CY7C1363C
Document #: 38-05541 Rev. *A
Page 14 of 30
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the bound-
ary scan register between the TDI and TDO pins.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells
prior to the selection of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases
can occur concurrently when required–that is, while data
captured is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO balls. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
TAP Timing
TAP AC Switching Characteristics
Over the Operating Range
[9, 10]
Parameter
Clock
t
TCYC
t
TF
t
TH
t
TL
Output Times
t
TDOV
t
TDOX
Setup Times
t
TMSS
t
TDIS
t
CS
Hold Times
t
TMSH
t
TDIH
t
CH
Notes:
9. t
and t
refer to the setup and hold time requirements of latching data from the boundary scan register.
10.Test conditions are specified using the load in TAP AC test conditions. t
R
/t
F
= 1 ns.
Parameter
Min.
Max.
Unit
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH time
TCK Clock LOW time
50
ns
MHz
ns
ns
20
25
25
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
5
ns
ns
0
TMS Set-Up to TCK Clock Rise
TDI Set-Up to TCK Clock Rise
Capture Set-Up to TCK Rise
5
5
5
ns
ns
TMS hold after TCK Clock Rise
TDI Hold after Clock Rise
Capture Hold after Clock Rise
5
5
5
ns
ns
ns
tTL
Test Clock
(TCK)
1
2
3
4
5
6
Test Mode Select
(TMS)
tTH
Test Data-Out
(TDO)
tCYC
Test Data-In
(TDI)
tTMSH
tTMSS
tTDIH
tTDIS
tTDOX
tTDOV
DON’T CARE
UNDEFINED
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| CY7C1361C-117BZI | 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1361C-133AJXC | 功能描述:靜態(tài)隨機存取存儲器 256Kx36 3.3V COM Sync FT 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1361C-133AJXCKJ | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1361C-133AJXCT | 功能描述:靜態(tài)隨機存取存儲器 256Kx36 3.3V COM Sync FT 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1361C-133AXC | 功能描述:靜態(tài)隨機存取存儲器 256Kx36 3.3V COM Sync FT 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1361C-133AXCKJ | 制造商:Cypress Semiconductor 功能描述: |
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