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參數(shù)資料
| 型號： | CY7C1361C-117BGC |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM |
| 中文描述： | 9兆位（256 × 36/512K × 18）流通過的SRAM |
| 文件頁數(shù)： | 10/30頁 |
| 文件大小： | 491K |
| 代理商： | CY7C1361C-117BGC |
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PRELIMINARY
CY7C1361C
CY7C1363C
Document #: 38-05541 Rev. *A
Page 10 of 30
ZZ Mode Electrical Characteristics
Parameter
I
DDZZ
t
ZZS
t
ZZREC
t
ZZI
t
RZZI
Truth Table
[ 3, 4, 5, 6, 7]
Description
Test Conditions
ZZ > V
DD
– 0.2V
ZZ > V
DD
– 0.2V
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
Min.
Max.
35
2t
CYC
Unit
mA
ns
ns
ns
ns
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ active to sleep current
ZZ Inactive to exit sleep current
2t
CYC
2t
CYC
0
Cycle Description
Address
Used
CE
1
H
CE
2
CE
3
ZZ
X
ADSP
ADSC
ADV WRITE OE CLK
DQ
Deselected Cycle, Power-down
None
X
L
X
L
X
X
X
L-H
three-state
Deselected Cycle, Power-down
None
L
L
X
L
L
X
X
X
X
L-H
three-state
Deselected Cycle, Power-down
None
L
X
H
L
L
X
X
X
X
L-H
three-state
Deselected Cycle, Power-down
None
L
L
X
L
H
L
X
X
X
L-H
three-state
Deselected Cycle, Power-down
None
X
X
X
L
H
L
X
X
X
L-H
three-state
Sleep Mode, Power-down
None
X
X
X
H
X
X
X
X
X
X
three-state
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
External
External
External
External
External
Next
Next
Next
L
L
L
L
L
X
X
H
H
H
H
H
H
X
X
X
L
L
L
L
L
X
X
X
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
X
X
X
L
L
L
H
H
H
X
X
X
X
X
L
L
L
X
X
L
H
H
H
H
H
L
H
X
L
H
L
H
L
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
Q
three-state
D
Q
three-state
Q
three-state
Q
Read Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
H
L-H
three-state
Write Cycle, Continue Burst
Next
X
X
X
L
H
H
L
L
X
L-H
D
Write Cycle, Continue Burst
Next
H
X
X
L
X
H
L
L
X
L-H
D
Read Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
L
L-H
Q
Read Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
H
L-H
three-state
Read Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
L
L-H
Q
Read Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
H
L-H
three-state
Write Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
L
X
L-H
D
Write Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
L
X
L-H
D
Notes:
3. X=”Don't Care.” H = Logic HIGH, L = Logic LOW.
4. WRITE = L when any one or more Byte Write enable signals and BWE = L or GW= L. WRITE = H when all Byte write enable signals , BWE, GW = H..
5. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW
. Writes may occur only on subsequent clocks after
the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. OE is a don't
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are three-state when OE
is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
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| CY7C1361C-133AJXC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 256Kx36 3.3V COM Sync FT 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1361C-133AJXCKJ | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1361C-133AJXCT | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 256Kx36 3.3V COM Sync FT 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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| CY7C1361C-133AXCKJ | 制造商:Cypress Semiconductor 功能描述: |
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