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參數(shù)資料
| 型號： | CY7C1353F |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 4-Mb (256K x 18) Flow-through SRAM with NoBL Architecture |
| 中文描述： | 4字節(jié)（256 × 18）流通過總線延遲結(jié)構(gòu)的SRAM |
| 文件頁數(shù)： | 9/13頁 |
| 文件大?。?/td> | 324K |
| 代理商： | CY7C1353F |
CY7C1353F
Document #: 38-05212 Rev. *B
Page 9 of 13
Switching Characteristics
Over the Operating Range
[16, 17]
Parameter
t
POWER
Clock
t
CYC
t
CH
t
CL
Output Times
t
CDV
t
DOH
t
CLZ
t
CHZ
t
OEV
t
OELZ
t
OEHZ
Set-up Times
t
AS
t
ALS
t
WES
t
CENS
t
DS
t
CES
Hold Times
t
AH
t
ALH
t
WEH
t
CENH
t
DH
t
CEH
Shaded areas contain advance information.
Description
133 MHz
Min.
1
117 MHz
Min.
1
100 MHz
Min.
1
66 MHz
Min.
1
Unit
ms
Max.
Max.
Max.
Max.
V
DD
(Typical) to the first Access
[12]
Clock Cycle Time
Clock HIGH
Clock LOW
7.5
2.5
2.5
8.5
3.0
3.0
10
4.0
4.0
15
5.0
5.0
ns
ns
ns
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
Clock to Low-Z
[13, 14, 15]
Clock to High-Z
13, 14, 15]
6.5
7.5
8.0
11.0
ns
ns
ns
ns
ns
ns
ns
2.0
0
2.0
0
2.0
0
2.0
0
3.5
3.5
3.5
3.5
3.5
3.5
5.0
6.0
OE LOW to Output Valid
OE LOW to Output Low-Z
[13, 14, 15]
OE HIGH to Output High-Z
[13, 14, 15]
0
0
0
0
3.5
3.5
3.5
6.0
Address Set-up Before CLK Rise
1.5
1.5
1.5
1.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
ns
ns
ns
ns
ns
ns
ADV/LD Set-up Before CLK Rise
WE, BW
[A:B]
Set-Up Before CLK Rise
CEN Set-up Before CLK Rise
Data Input Set-up Before CLK Rise
Chip Enable Set-Up Before CLK Rise
Address Hold After CLK Rise
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
ADV/LD Hold after CLK Rise
WE, BW
[A:B]
Hold After CLK Rise
CEN Hold After CLK Rise
Data Input Hold After CLK Rise
Chip Enable Hold After CLK Rise
Notes:
12.This part has a voltage regulator internally; t
power
is the time that the power needs to be supplied above V
DD
minimum initially before a read or write operation
can be initiated.
13.t
, t
,t
, and t
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
14.At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve Three-state prior to Low-Z under the same system conditions.
15.This parameter is sampled and not 100% tested.
16.Timing reference level is 1.5V when V
=3.3V and is 1.25V when V
DDQ
=2.5V.
17.Test conditions shown in (a) of AC Test Loads, unless otherwise noted.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| CY7C1353F-100AC | 功能描述:IC SRAM 4.5MBIT 100MHZ 100LQFP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:96 系列:- 格式 - 存儲器:閃存 存儲器類型:FLASH 存儲容量:16M（2M x 8，1M x 16） 速度:70ns 接口:并聯(lián) 電源電壓:2.65 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應(yīng)商設(shè)備封裝:48-TSOP 包裝:托盤 |
| CY7C1353F-100ACT | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Single 3.3V 4.5M-Bit 256K x 18 8ns 100-Pin TQFP T/R 制造商:Rochester Electronics LLC 功能描述:4M- 256KX18 3.3V FLOW-THROUGH-NOBL SRAM - Tape and Reel |
| CY7C1353G-100AXC | 功能描述:靜態(tài)隨機存取存儲器 256Kx18 3.3V NoBL Sync PL 靜態(tài)隨機存取存儲器 COM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1353G-100AXCT | 功能描述:靜態(tài)隨機存取存儲器 256Kx18 3.3V NoBL Sync PL 靜態(tài)隨機存取存儲器 COM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1353G-133AXC | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述: |
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