參數(shù)資料
型號: CY7C1353F
廠商: Cypress Semiconductor Corp.
英文描述: 4-Mb (256K x 18) Flow-through SRAM with NoBL Architecture
中文描述: 4字節(jié)(256 × 18)流通過總線延遲結(jié)構(gòu)的SRAM
文件頁數(shù): 11/13頁
文件大?。?/td> 324K
代理商: CY7C1353F
CY7C1353F
Document #: 38-05212 Rev. *B
Page 11 of 13
Notes:
18.For this waveform ZZ is tied low.
19.When CE is LOW, CE
is LOW, CE
is HIGH and CE
is LOW. When CE is HIGH, CE
is HIGH or CE
is LOW or CE
is HIGH.
20.Order of the Burst sequence is determined by the status of the MODE (0= Linear, 1= Interleaved). Burst operations are optional.
21.The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrates CEN being used to create a pause. A write is not performed during this cycle.
22.Device must be deselected when entering ZZ mode. See truth table for all possible signal conditions to deselect the device.
23.DQs are in high-Z when exiting ZZ sleep mode.
NOP, STALL and DESELECT Cycles
[18, 19, 21]
1
ZZ Mode Timing
[22,23]
Switching Waveforms
READ
Q(A3)
4
5
6
7
8
9
10
A3
A4
A5
D(A4)
2
3
CLK
CE
WE
CEN
BW
[A:B]
ADV/LD
ADDRESS
DQ
COMMAND
WRITE
D(A4)
STALL
WRITE
D(A1)
READ
Q(A2)
STALL
NOP
READ
Q(A5)
DESELECT
CONTINUE
DESELECT
DON’T CARE
UNDEFINED
tCHZ
A1
A2
Q(A2)
D(A1)
Q(A3)
tDOH
Q(A5)
tZZ
I
SUPPLY
CLK
ZZ
tZZREC
ALL INPUTS
(except ZZ)
DON’T CARE
IDDZZ
tZZI
tRZZI
Outputs (Q)
High-Z
DESELECT or READ Only
相關(guān)PDF資料
PDF描述
CY7C1353F-100AC 4-Mb (256K x 18) Flow-through SRAM with NoBL Architecture
CY7C1353F-100AI 4-Mb (256K x 18) Flow-through SRAM with NoBL Architecture
CY7C1353F-117AC 4-Mb (256K x 18) Flow-through SRAM with NoBL Architecture
CY7C1353F-117AI 4-Mb (256K x 18) Flow-through SRAM with NoBL Architecture
CY7C1353F-133AC 4-Mb (256K x 18) Flow-through SRAM with NoBL Architecture
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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