參數(shù)資料
型號(hào): CY7C1353F
廠商: Cypress Semiconductor Corp.
英文描述: 4-Mb (256K x 18) Flow-through SRAM with NoBL Architecture
中文描述: 4字節(jié)(256 × 18)流通過(guò)總線延遲結(jié)構(gòu)的SRAM
文件頁(yè)數(shù): 7/13頁(yè)
文件大?。?/td> 324K
代理商: CY7C1353F
CY7C1353F
Document #: 38-05212 Rev. *B
Page 7 of 13
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on V
DD
Relative to GND........–0.5V to +4.6V
DC Voltage Applied to Outputs
in three-state....................................... –0.5V to V
DDQ
+ 0.5V
DC Input Voltage....................................–0.5V to V
DD
+ 0.5V
Electrical Characteristics
Over the Operating Range
[9,10]
Current into Outputs (LOW).........................................20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.................................................... > 200 mA
Operating Range
Range
Com’l
Ind’l
Ambient
Temperature (T
A
)
0°C to +70°C
40°C to +85°C
V
DD
V
DDQ
3.3V – 5%/+10% 2.5V – 5% to
V
DD
Parameter
V
DD
V
DDQ
V
OH
Description
Test Conditions
Min.
3.135
2.375
2.4
2.0
Max.
3.6
V
DD
Unit
V
V
V
V
V
V
V
V
V
V
μ
A
Power Supply Voltage
I/O Supply Voltage
Output HIGH Voltage
V
DDQ
= 3.3V, V
DD
= Min., I
OH
= –4.0 mA
V
DDQ
= 2.5V, V
DD
= Min., I
OH
= –1.0 mA
V
DDQ
= 3.3V, V
DD
= Min., I
OH
= 8.0 mA
V
DDQ
= 2.5V, V
DD
= Min., I
OH
= 1.0 mA
V
DDQ
= 3.3V
V
DDQ
= 2.5V
V
DDQ
= 3.3V
V
DDQ
= 2.5V
GND
V
I
V
DDQ
V
OL
Output LOW Voltage
0.4
0.4
V
IH
Input HIGH Voltage
Input HIGH Voltage
Input LOW Voltage
[9]
Input LOW Voltage
[9]
Input Load Current
(except ZZ and MODE)
Input Current of MODE
2.0
1.7
–0.3
–0.3
5
V
DD
+ 0.3V
V
DD
+ 0.3V
0.8
0.7
5
V
IL
I
X
Input = V
SS
Input = V
DD
Input = V
SS
Input = V
DD
GND
V
I
V
DD
, Output Disabled
–30
μ
A
μ
A
μ
A
μ
A
μ
A
μ
A
mA
mA
mA
mA
mA
mA
mA
mA
mA
5
Input Current of ZZ
–5
30
5
–300
225
220
205
195
90
85
80
60
40
I
OZ
I
OS
I
DD
Output Leakage Current
Output Short Circuit Current V
DD
= Max., V
OUT
= GND
V
DD
Operating Supply
Current
–5
V
DD
= Max., I
OUT
= 0 mA,
f = f
MAX
= 1/t
CYC
7.5-ns cycle, 133 MHz
8.5-ns cycle, 117 MHz
10-ns cycle, 100 MHz
15-ns cycle, 66 MHz
7.5-ns cycle, 133 MHz
8.5-ns cycle, 117 MHz
10-ns cycle, 100 MHz
15-ns cycle, 66 MHz
All speeds
I
SB1
Automatic CE Power-down
Current—TTL Inputs
V
DD
= Max, Device Deselected,
V
IN
V
IH
or V
IN
V
IL
, f = f
MAX
,
inputs switching
I
SB2
Automatic CE Power-down
Current—CMOS Inputs
V
DD
= Max, Device Deselected,
V
IN
V
DD
– 0.3V or V
IN
0.3V,
f = 0, inputs static
Shaded areas contain advance information.
Notes:
9. Overshoot: V
IH
(AC) < V
DD
+1.5V (Pulse width less than t
CYC
/2), undershoot: V
IL
(AC)> -2V (Pulse width less than t
CYC
/2).
10.T
Power-up
: Assumes a linear ramp from 0V to V
DD
(min.) within 200ms. During this time V
IH
< V
DD
and V
DDQ
< V
DD
.
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CY7C1353F-100AC 4-Mb (256K x 18) Flow-through SRAM with NoBL Architecture
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