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參數(shù)資料
| 型號(hào)： | CY7C1353F |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 4-Mb (256K x 18) Flow-through SRAM with NoBL Architecture |
| 中文描述： | 4字節(jié)（256 × 18）流通過總線延遲結(jié)構(gòu)的SRAM |
| 文件頁(yè)數(shù)： | 4/13頁(yè) |
| 文件大小： | 324K |
| 代理商： | CY7C1353F |
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CY7C1353F
Document #: 38-05212 Rev. *B
Page 4 of 13
Functional Overview
The CY7C1353F is a synchronous flow-through burst SRAM
designed specifically to eliminate wait states during
Write-Read transitions. All synchronous inputs pass through
input registers controlled by the rising edge of the clock. The
clock signal is qualified with the Clock Enable input signal
(CEN). If CEN is HIGH, the clock signal is not recognized and
all internal states are maintained. All synchronous operations
are qualified with CEN. Maximum access delay from the clock
rise (t
CDV
) is 6.5 ns (133-MHz device).
Accesses can be initiated by asserting all three Chip Enables
(CE
1
, CE
2
, CE
3
) active at the rising edge of the clock. If Clock
Enable (CEN) is active LOW and ADV/LD is asserted LOW,
the address presented to the device will be latched. The
access can either be a read or write operation, depending on
the status of the Write Enable (WE). BW
[A:B]
can be used to
conduct byte write operations.
Write operations are qualified by the Write Enable (WE). All
writes are simplified with on-chip synchronous self-timed write
circuitry.
Three synchronous Chip Enables (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) simplify depth expansion.
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD should be driven LOW once the device has been
deselected in order to load a new address for the next
operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE
1
, CE
2
,
and CE
3
are ALL asserted active, (3) the Write Enable input
signal WE is deasserted HIGH, and 4) ADV/LD is asserted
LOW. The address presented to the address inputs is latched
into the Address Register and presented to the memory array
and control logic. The control logic determines that a read
access is in progress and allows the requested data to
propagate to the output buffers. The data is available within 6.5
ns (133-MHz device) provided OE is active LOW. After the first
clock of the read access, the output buffers are controlled by
OE and the internal control logic. OE must be driven LOW in
order for the device to drive out the requested data. On the
subsequent clock, another operation (Read/Write/Deselect)
can be initiated. When the SRAM is deselected at clock rise
by one of the chip enable signals, its output will be three-stated
immediately.
Burst Read Accesses
The CY7C1353F has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Reads without reasserting the address inputs. ADV/LD
must be driven LOW in order to load a new address into the
SRAM, as described in the Single Read Access section above.
The sequence of the burst counter is determined by the MODE
input signal. A LOW input on MODE selects a linear burst
mode, a HIGH selects an interleaved burst sequence. Both
burst counters use A0 and A1 in the burst sequence, and will
wrap around when incremented sufficiently. A HIGH input on
ADV/LD will increment the internal burst counter regardless of
the state of chip enable inputs or WE. WE is latched at the
beginning of a burst cycle. Therefore, the type of access (Read
or Write) is maintained throughout the burst sequence.
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE
1
, CE
2
,
and CE
3
are ALL asserted active, and (3) the write signal WE
is asserted LOW. The address presented to the address bus
is loaded into the Address Register. The write signals are
latched into the Control Logic block. The data lines are
automatically three-stated regardless of the state of the OE
input signal. This allows the external logic to present the data
on DQs and DQP
[A:B]
.
On the next clock rise the data presented to DQs and DQP
[A:B]
(or a subset for byte write operations, see truth table for
details) inputs is latched into the device and the write is
complete. Additional accesses (Read/Write/Deselect) can be
initiated on this cycle.
The data written during the Write operation is controlled by
BW
[A:B]
signals. The CY7C1353F provides byte write
capability that is described in the truth table. Asserting the
Write Enable input (WE) with the selected Byte Write Select
input will selectively write to only the desired bytes. Bytes not
selected during a byte write operation will remain unaltered. A
synchronous self-timed write mechanism has been provided
to simplify the write operations. Byte write capability has been
included in order to greatly simplify Read/Modify/Write
sequences, which can be reduced to simple byte write opera-
tions.
Because the CY7C1353F is a common I/O device, data should
not be driven into the device while the outputs are active. The
Output Enable (OE) can be deasserted HIGH before
presenting data to the DQs and DQP
[A:B]
inputs. Doing so will
three-state the output drivers. As a safety precaution, DQs and
DQP
[A:B]
.are automatically three-stated during the data
portion of a write cycle, regardless of the state of OE.
Burst Write Accesses
The CY7C1353F has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Write operations without reasserting the address inputs.
ADV/LD must be driven LOW in order to load the initial
address, as described in the Single Write Access section
above. When ADV/LD is driven HIGH on the subsequent clock
rise, the Chip Enables (CE
1
, CE
2
, and CE
3
) and WE inputs are
ignored and the burst counter is incremented. The correct
NC
1,2,3,6,7,14,16,
25,28,29,30,38,
39,42,43,51,52,
53,56,57,66,75,
78,79,83,84,95,
96
–
No Connects
. Not Internally connected to the die.
9M,18M,36M and 72M are address expansion pins and are not internally
connected to the die.
Pin Definitions
(100-pin TQFP Package) (continued)
Name
TQFP
I/O
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1353F-100AC | 4-Mb (256K x 18) Flow-through SRAM with NoBL Architecture |
| CY7C1353F-100AI | 4-Mb (256K x 18) Flow-through SRAM with NoBL Architecture |
| CY7C1353F-117AC | 4-Mb (256K x 18) Flow-through SRAM with NoBL Architecture |
| CY7C1353F-117AI | 4-Mb (256K x 18) Flow-through SRAM with NoBL Architecture |
| CY7C1353F-133AC | 4-Mb (256K x 18) Flow-through SRAM with NoBL Architecture |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1353F-100AC | 功能描述:IC SRAM 4.5MBIT 100MHZ 100LQFP RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:96 系列:- 格式 - 存儲(chǔ)器:閃存 存儲(chǔ)器類型:FLASH 存儲(chǔ)容量:16M（2M x 8，1M x 16） 速度:70ns 接口:并聯(lián) 電源電壓:2.65 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應(yīng)商設(shè)備封裝:48-TSOP 包裝:托盤 |
| CY7C1353F-100ACT | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Single 3.3V 4.5M-Bit 256K x 18 8ns 100-Pin TQFP T/R 制造商:Rochester Electronics LLC 功能描述:4M- 256KX18 3.3V FLOW-THROUGH-NOBL SRAM - Tape and Reel |
| CY7C1353G-100AXC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 256Kx18 3.3V NoBL Sync PL 靜態(tài)隨機(jī)存取存儲(chǔ)器 COM RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1353G-100AXCT | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 256Kx18 3.3V NoBL Sync PL 靜態(tài)隨機(jī)存取存儲(chǔ)器 COM RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1353G-133AXC | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述: |
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