參數(shù)資料
型號: CY7C1353F
廠商: Cypress Semiconductor Corp.
英文描述: 4-Mb (256K x 18) Flow-through SRAM with NoBL Architecture
中文描述: 4字節(jié)(256 × 18)流通過總線延遲結構的SRAM
文件頁數(shù): 5/13頁
文件大小: 324K
代理商: CY7C1353F
CY7C1353F
Document #: 38-05212 Rev. *B
Page 5 of 13
BW
[A:B]
inputs must be driven in each cycle of the burst write,
in order to write the correct bytes of data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE
1
, CE
2
, and CE
3
, must remain inactive for
the duration of t
ZZREC
after the ZZ input returns LOW.
Linear Burst Address Table (MODE = GND)
First
Address
A1, A0
00
01
10
11
Second
Address
A1, A0
01
10
11
00
Third
Address
A1, A0
10
11
00
01
Fourth
Address
A1, A0
11
00
01
10
Interleaved Burst Address Table (MODE =
Floating or V
DD
)
First
Address
A1, A0
A1, A0
00
01
01
00
10
11
11
10
Second
Address
Third
Address
A1, A0
10
11
00
01
Fourth
Address
A1, A0
11
10
01
00
ZZ Mode Electrical Characteristics
Parameter
I
DDZZ
t
ZZS
t
ZZREC
t
ZZI
t
RZZI
Description
Test Conditions
Min.
Max.
40
2t
CYC
Unit
mA
ns
ns
ns
ns
Snooze mode standby current
Device operation to ZZ
ZZ recovery time
ZZ active to snooze current
ZZ inactive to exit snooze current
ZZ > V
DD
0.2V
ZZ > V
DD
0.2V
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
2t
CYC
2t
CYC
0
Truth Table
[2, 3, 4, 5, 6, 7, 8]
Operation
ADDRESS
Used
CE
1
H
CE
2
X
CE
3
X
ZZ
ADV/LD
WE
BW
X
X
OE
CEN
CLK
DQ
Deselect Cycle
None
L
L
X
X
L
L->H
three-state
Deselect Cycle
None
X
X
H
L
L
X
X
X
L
L->H
three-state
Deselect Cycle
None
X
L
X
L
L
X
X
X
L
L->H
three-state
Continue Deselect Cycle
None
X
X
X
L
H
X
X
X
L
L->H
three-state
READ Cycle
(Begin Burst)
External
L
H
L
L
L
H
X
L
L
L->H Data Out (Q)
READ Cycle
(Continue Burst)
Next
X
X
X
L
H
X
X
L
L
L->H Data Out (Q)
NOP/DUMMY READ
(Begin Burst)
External
L
H
L
L
L
H
X
H
L
L->H
three-state
DUMMY READ
(Continue Burst)
Next
X
X
X
L
H
X
X
H
L
L->H
three-state
WRITE Cycle
(Begin Burst)
External
L
H
L
L
L
L
L
X
L
L->H Data In (D)
Notes:
2. X =”Don't Care.” H = Logic HIGH, L = Logic LOW. BWx = 0 signifies at least one Byte Write Select is active, BWx = Valid signifies that the desired byte write
selects are asserted, see truth table for details.
3. Write is defined by BW
, and WE. See truth table for Read/Write.
4. When a write cycle is detected, all I/Os are three-stated, even during byte writes.
5. The DQs and DQP
pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. CEN = H, inserts wait states.
7. Device will power-up deselected and the I/Os in a three-state condition, regardless of OE.
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP
[A:B]
= Three-state when
OE is inactive or when the device is deselected, and DQs and DQP
[A:B]
= data when OE is active.
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CY7C1353F-100AC 4-Mb (256K x 18) Flow-through SRAM with NoBL Architecture
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