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參數(shù)資料
| 型號： | CY7C1024DV33-8BGXC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 3-Mbit (128K X 24) Static RAM |
| 中文描述： | 128K X 24 STANDARD SRAM, 8 ns, PBGA119 |
| 封裝： | 14 X 22 MM, 2.40 MM HEIGHT, LEAD FREE, PLASTIC, BGA-119 |
| 文件頁數(shù)： | 6/8頁 |
| 文件大小： | 295K |
| 代理商： | CY7C1024DV33-8BGXC |
PRELIMINARY
CY7C1024DV33
Document #: 001-08353 Rev. *A
Page 6 of 8
Write Cycle No. 1 (CE Controlled)
[14, 17, 18]
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)
[14, 17, 18]
Write Cycle No. 3 (WE Controlled, OE LOW)
[14, 18]
Notes:
17.Data I/O is high impedance if OE = V
.
18.If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
19.During this period the I/Os are in the output state and input signals should not be applied.
Switching Waveforms
(continued)
t
WC
DATA VALID
t
AW
t
SA
t
PWE
t
HA
t
HD
t
SD
t
SCE
t
SCE
CE
ADDRESS
WE
DATA I/O
t
HD
t
SD
t
PWE
t
SA
t
HA
t
AW
t
SCE
t
WC
t
HZOE
DATA
IN
VALID
CE
ADDRESS
WE
DATA I/O
OE
NOTE
19
DATA VALID
t
HD
t
SD
t
LZWE
t
PWE
t
SA
t
HA
t
AW
t
SCE
t
WC
t
HZWE
CE
ADDRESS
WE
DATA I/O
NOTE
19
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