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參數(shù)資料
| 型號： | CY7C1024DV33-8BGXC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 3-Mbit (128K X 24) Static RAM |
| 中文描述： | 128K X 24 STANDARD SRAM, 8 ns, PBGA119 |
| 封裝： | 14 X 22 MM, 2.40 MM HEIGHT, LEAD FREE, PLASTIC, BGA-119 |
| 文件頁數(shù)： | 1/8頁 |
| 文件大?。?/td> | 295K |
| 代理商： | CY7C1024DV33-8BGXC |
PRELIMINARY
3-Mbit (128K X 24) Static RAM
CY7C1024DV33
Cypress Semiconductor Corporation
Document #: 001-08353 Rev. *A
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised September 4, 2006
Features
High speed
— t
AA
= 8 ns
Low active power
— I
CC
= 185 mA @ 8 ns
Low CMOS standby power
— I
SB2
= 25 mA
Operating voltages of 3.3 ± 0.3V
2.0V data retention
Automatic power-down when deselected
TTL-compatible inputs and outputs
Easy memory expansion with CE
1
, CE
2
and CE
3
features
Available in Pb-Free Standard 119-ball PBGA
Functional Description
The CY7C1024DV33 is a high-performance CMOS static
RAM organized as 128K words by 24 bits. This device has an
automatic power-down feature that significantly reduces
power consumption when deselected.
To write to the device, enable the chip (CE
1
LOW, CE
2
HIGH
and CE
3
LOW) while forcing the Write Enable (WE) input
LOW.
To read from the device, enable the chip by taking CE
1
LOW
CE
2
HIGH and CE
3
LOW while forcing the Output Enable (OE)
LOW and the Write Enable (WE) HIGH. See the truth table at
the back of this data sheet for a complete description of Read
and Write modes.
The 24 I/O pins (I/O
0
–I/O
23
) are placed in a high-impedance
state when all the chip selects are HIGH or when the output
enable (OE) is HIGH during a READ mode. For further details,
refer to the truth table of this data sheet.
Selection Guide
–8
8
185
25
Unit
ns
mA
mA
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Functional Block Diagram
1
A
1
A
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
COLUMN
DECODER
R
S
INPUT BUFFER
128K x 24
ARRAY
A
0
A
1
A
1
A
1
A
1
A
1
OE
I/O
0
–I/O
23
CE
1
, CE
2
, CE
3
WE
CONTROL LOGIC
[+] Feedback
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