參數(shù)資料
型號： CY7C1024DV33-8BGXC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： DRAM
英文描述： 3-Mbit (128K X 24) Static RAM
中文描述： 128K X 24 STANDARD SRAM, 8 ns, PBGA119
封裝： 14 X 22 MM, 2.40 MM HEIGHT, LEAD FREE, PLASTIC, BGA-119
文件頁數(shù)： 3/8頁
文件大小： 295K
代理商： CY7C1024DV33-8BGXC
PRELIMINARY
CY7C1024DV33
Document #: 001-08353 Rev. *A
Page 3 of 8
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–65
°
C to +150
°
C
Ambient Temperature with
Power Applied.............................................–55
°
C to +125
°
C
Supply Voltage on V
CC
Relative to GND
[2]
....–0.5V to +4.6V
DC Voltage Applied to Outputs
in High-Z State
[2]
....................................–0.5V to V
CC
+ 0.5V
DC Input Voltage
[2]
.................................–0.5V to V
CC
+ 0.5V
DC Electrical Characteristics
Over the Operating Range
Current into Outputs (LOW).........................................20 mA
Static Discharge Voltage............................................>2001V
(per MIL-STD-883, Method 3015)
Latch-up Current......................................................>200 mA
Operating Range
Range
Ambient
Temperature
0
°
C to +70
°
C
V
CC
Commercial
3.3V
±
0.3V
Parameter
V
OH
V
OL
V
IH
V
IL[2]
I
IX
I
OZ
I
CC
Description
Test Conditions
[7]
V
CC
= Min., I
OH
= –4.0 mA
V
CC
= Min., I
OL
= 8.0 mA
–8
Unit
V
V
V
V
μ
A
μ
A
mA
Min.
2.4
Max.
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage Current
Output Leakage Current
V
CC
Operating Supply Current
0.4
2.0
–0.3
–1
–1
V
CC
+ 0.3
0.8
+1
+1
185
GND < V
I
< V
CC
GND < V
OUT
< V
CC
, Output Disabled
V
CC
= Max., f = f
MAX
= 1/t
RC
I
OUT
= 0 mA CMOS levels
Max. V
CC
, CE > V
IH
V
IN
> V
IH
or V
IN
< V
IL
, f = f
MAX
Max. V
CC
, CE > V
CC
– 0.3V,
V
IN
> V
CC
– 0.3V, or V
IN
< 0.3V, f = 0
I
SB1
Automatic CE Power-down
Current —TTL Inputs
Automatic CE Power-down
Current —CMOS Inputs
30
mA
I
SB2
25
mA
Capacitance
[3]
Parameter
Description
Test Conditions
Max.
8
10
Unit
pF
pF
C
IN
C
OUT
Input Capacitance
I/O Capacitance
T
A
= 25
°
C, f = 1 MHz, V
CC
= 3.3V
Thermal Resistance
[3]
Parameter
Θ
JA
Θ
JC
Description
Test Conditions
PBGA
TBD
TBD
Unit
°
C/W
°
C/W
Thermal Resistance (Junction to Ambient) Still Air, soldered on a 3 × 4.5 inch,
Thermal Resistance (Junction to Case)
four-layer printed circuit board
AC Test Loads and Waveforms
[4]
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
3.3V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(b)
R1 317
R2
351
Rise time > 1 V/ns
Fall time: > 1 V/ns
(c)
50
Notes:
2. V
(min.) = –2.0V and V
(max) = V
+ 2V for pulse durations of less than 20 ns.
3. Tested initially and after any design or process changes that may affect these parameters.
4. Valid SRAM operation does not occur until the power supplies have reached the minimum operating V
DD
(3.0V). 100
μ
s (t
power
) after reaching the minimum
operating V
DD
, normal SRAM operation can begin including reduction in V
DD
to the data retention (V
CCDR
, 2.0V) voltage.
(a)
OUTPUT
Z
0
= 50
V
TH
= 1.5V
30 pF** Capacitive Load consists of all
components of the test environment.
[+] Feedback
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