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參數(shù)資料
| 型號(hào)： | CY7C1024DV33-8BGXC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 3-Mbit (128K X 24) Static RAM |
| 中文描述： | 128K X 24 STANDARD SRAM, 8 ns, PBGA119 |
| 封裝： | 14 X 22 MM, 2.40 MM HEIGHT, LEAD FREE, PLASTIC, BGA-119 |
| 文件頁(yè)數(shù)： | 4/8頁(yè) |
| 文件大?。?/td> | 295K |
| 代理商： | CY7C1024DV33-8BGXC |
PRELIMINARY
CY7C1024DV33
Document #: 001-08353 Rev. *A
Page 4 of 8
AC Switching Characteristics
Over the Operating Range
[5]
Parameter
Description
–8
Unit
Min.
Max.
Read Cycle
t
power[6]
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
Write Cycle
[10, 11]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
Notes:
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V. Test conditions for the read cycle use
output loading as shown in part a) of the AC test loads, unless specified otherwise.
6. t
gives the minimum amount of time that the power supply should be at typical V
values until the first memory access is performed.
7. CE refers to a combination of CE
, CE
2
, and CE
3
. CE is active LOW when CE
1
is LOW and CE
2
is HIGH and CE
3
is LOW. CE is deselect HIGH when CE
1
is
HIGH or CE
2
is LOW or CE
3
is HIGH
8. t
, t
, t
, and t
LZOE
, t
LZCE
, t
LZWE
, are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured
±
200 mV from
steady-state voltage.
9. These parameters are guaranteed by design and are not tested.
10.The internal write time of the memory is defined by the overlap of CE
and CE
and CE
LOW and WE LOW. The chip enables must be active and WE must be
LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading
edge of the signal that terminates the write.
11. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
V
CC
(typical) to the first access
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE
active LOW to Data Valid
[7]
OE LOW to Data Valid
OE LOW to Low-Z
[8]
OE HIGH to High-Z
[8]
CE
active LOW to Low-Z
[7, 8]
CE deselect
HIGH to High-Z
[7, 8]
CE
active LOW to Power-up
[7, 9]
CE deselect
HIGH to Power-down
[7, 9]
100
8
μ
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
8
3
8
5
1
5
3
5
0
8
Write Cycle Time
CE
active LOW to Write End
[7]
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
Data Set-up to Write End
Data Hold from Write End
WE HIGH to Low-Z
[8]
WE LOW to High-Z
[8]
8
6
6
0
0
6
5
0
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
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