參數(shù)資料
型號(hào)： CY7C1031-8JC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： DRAM
英文描述： 64K x 18 Synchronous Cache RAM
中文描述： 64K X 18 CACHE SRAM, 8.5 ns, PQCC52
封裝： PLASTIC, LCC-52
文件頁(yè)數(shù)： 1/13頁(yè)
文件大小： 282K
代理商： CY7C1031-8JC
64K x 18 Synchronous Cache RAM
CY7C1031
CY7C1032
Cypress Semiconductor Corporation
Document #: 38-05278 Rev. *A
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised April 1, 2004
Features
Supports 66-MHz Pentium
microprocessor cache
systems with zero wait states
64K by 18 common I/O
Fast clock-to-output times
— 8.5 ns
Two-bit wraparound counter supporting Pentium
microprocessor and 486 burst sequence (CY7C1031)
Two-bit wraparound counter supporting linear burst
sequence (CY7C1032)
Separate processor and controller address strobes
Synchronous self-timed write
Direct interface with the processor and external cache
controller
Asynchronous output enable
I/Os capable of 3.3V operation
JEDEC-standard pinout
52-pin PLCC packaging
Logic Block Diagram
Functional Description
The CY7C1031 and CY7C1032 are 64K by 18 synchronous
cache RAMs designed to interface with high-speed micropro-
cessors with minimum glue logic. Maximum access delay from
clock rise is 8.5 ns. A 2-bit on-chip counter captures the first
address in a burst and increments the address automatically
for the rest of the burst access.
The CY7C1031 is designed for Intel
Pentium and i486
CPU-based systems; its counter follows the burst sequence of
the Pentium and the i486 processors. The CY7C1032 is archi-
tected for processors with linear burst sequences. Burst
accesses can be initiated with the processor address strobe
(ADSP) or the cache controller address strobe (ADSC) inputs.
Address advancement is controlled by the address
advancement (ADV) input.
A synchronous self-timed write mechanism is provided to
simplify the write interface. A synchronous chip select input
and an asynchronous output enable input provide easy control
for bank selection and output three-state control.
Selection Guide
7C1031-8
7C1032-8
8.5
280
7C1031-10
7C1032-10
10
280
7C1031-12
Unit
ns
mA
Maximum Access Time
Maximum Operating Current
12
230
Commercial
Note:
1. DP
0
and DP
1
are functionally equivalent to DQ
x
.
Pin Configuration
PLCC
Top View
18
16
14
14
2
2
16
9
9
9
9
18
CLK
TIMING
ADDR
REG
LADV
REGISTER
R64K X 9
R64K X 9
OE
1
7C1031
8
9
10
11
12
13
14
15
16
17
18
19
20
46
45
44
43
42
41
40
39
38
37
36
35
34
2122 23 24 25 26 27 28 29 30 31 32 33
7 6 5 4 3 2
52 51 50 49 48 47
A
5
A
A
3
A
2
C
V
A
A
A
A
A
A
1
G
A
6
C
C
A
DQ
8
DQ
9
V
CCQ
V
SSQ
DQ
10
DQ
11
DQ
12
DQ
13
V
SSQ
V
CCQ
DQ
14
DQ
15
DP
1
A
9
A
7
DP
0
DQ
7
DQ
6
V
CCQ
V
SSQ
DQ
5
DQ
4
DQ
3
DQ
2
V
SSQ
V
CCQ
DQ
1
DQ
0
A
8
O
A
A
A
W
W
A
15
–A
0
DATA
IN
ADSP
ADSC
CS
WH
WL
WH
WL
DQ
15
– DQ
0
DP
1
– DP
0
A
ADV
4
1
1
1
1
1
1
[1]
[1]
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PDF描述
CY7C1031-10JC 64K x 18 Synchronous Cache RAM
CY7C1031-12JC 64K x 18 Synchronous Cache RAM
CY7C1032-10JC 64K x 18 Synchronous Cache RAM
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CY7C1032-10JC 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Single 5V 1.125M-Bit 64K x 18 10ns 52-Pin PLCC 制造商:Rochester Electronics LLC 功能描述:1MB (64KX18) SYNCH RAM POWER PC BURST - Bulk
CY7C1032-10JCT 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Single 5V 1.125M-Bit 64K x 18 10ns 52-Pin PLCC T/R
CY7C1032-12JC 制造商:Rochester Electronics LLC 功能描述:- Bulk
CY7C10328JC 制造商:CYPRESS 功能描述:NEW
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