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參數(shù)資料
| 型號： | CY7C1024DV33-8BGXC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 3-Mbit (128K X 24) Static RAM |
| 中文描述： | 128K X 24 STANDARD SRAM, 8 ns, PBGA119 |
| 封裝： | 14 X 22 MM, 2.40 MM HEIGHT, LEAD FREE, PLASTIC, BGA-119 |
| 文件頁數(shù)： | 5/8頁 |
| 文件大小： | 295K |
| 代理商： | CY7C1024DV33-8BGXC |
PRELIMINARY
CY7C1024DV33
Document #: 001-08353 Rev. *A
Page 5 of 8
Data Retention Characteristics
(Over the Operating Range)
Parameter
V
DR
I
CCDR
Description
Conditions
Min.
2
Typ.
Max.
Unit
V
mA
V
CC
for Data Retention
Data Retention Current
V
CC
= 2V , CE
1
> V
CC
– 0.2V,
CE
2
< 0.2V, V
IN
> V
CC
– 0.2V or
V
IN
< 0.2V
25
t
CDR[3]
t
R[12]
Chip Deselect to Data Retention Time
Operation Recovery Time
0
ns
ns
t
RC
Data Retention Waveform
3V
3V
t
CDR
V
DR
> 2V
DATA RETENTION MODE
t
R
CE
V
CC
Switching Waveforms
Read Cycle No. 1
[13, 15]
Read Cycle No. 2 (OE Controlled)
[14, 15, 16]
Notes:
12.Full device operation requires linear V
ramp from V
DR
to V
CC(min.)
> 50
μ
s or stable at V
CC(min.)
> 50
μ
s
13.Device is continuously selected. OE, CE = V
.
14.CE refers to a combination of CE
1
, CE
2
, and CE
3
. CE is active LOW when CE
1
LOW and CE
2
HIGH and CE
3
LOW.
15.WE is HIGH for read cycle.
16.Address valid prior to or coincident with CE transition LOW.
PREVIOUS DATA VALID
DATA VALID
t
RC
t
AA
t
OHA
ADDRESS
DATA OUT
50%
50%
DATA VALID
t
RC
t
ACE
t
DOE
t
LZOE
t
LZCE
t
PU
HIGH IMPEDANCE
t
HZOE
t
HZCE
t
PD
HIGH
OE
CE
I
CC
I
SB
IMPEDANCE
ADDRESS
DATA OUT
V
CC
SUPPLY
CURRENT
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