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參數(shù)資料
| 型號： | CY62168DV3_06 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 16-Mbit (2M x 8) MoBL㈢ Static RAM |
| 中文描述： | 16兆位（2米× 8）的MoBL㈢靜態(tài)RAM |
| 文件頁數(shù)： | 5/9頁 |
| 文件大?。?/td> | 305K |
| 代理商： | CY62168DV3_06 |
CY62168DV30 MoBL
Document #: 38-05329 Rev. *F
Page 5 of 9
Switching Characteristics
Over the Operating Range
[10]
Parameter
Description
55 ns
Unit
Min.
Max.
Read Cycle
t
RC
Read Cycle Time
55
ns
t
AA
Address to Data Valid
55
ns
t
OHA
Data Hold from Address Change
10
ns
t
ACE
CE
1
LOW and CE
2
HIGH to Data Valid
55
ns
t
DOE
OE LOW to Data Valid
25
ns
t
LZOE
OE LOW to Low Z
[11]
5
ns
t
HZOE
OE HIGH to High Z
[11, 12]
20
ns
t
LZCE
CE
1
LOW and CE
2
HIGH to Low Z
[11]
10
ns
t
HZCE
CE
1
HIGH or CE
2
LOW to High Z
[11, 12]
20
ns
t
PU
CE
1
LOW and CE
2
HIGH to Power-Up
0
ns
t
PD
CE
1
HIGH or CE
2
LOW to Power-Down
55
ns
Write Cycle
[13]
t
WC
Write Cycle Time
55
ns
t
SCE
CE
1
LOW and CE
2
HIGH to Write End
40
ns
t
AW
Address Set-Up to Write End
40
ns
t
HA
Address Hold from Write End
0
ns
t
SA
Address Set-Up to Write Start
0
ns
t
PWE
WE Pulse Width
40
ns
t
SD
Data Set-Up to Write End
25
ns
t
HD
Data Hold from Write End
0
ns
t
HZWE
WE LOW to High Z
[11, 12]
20
ns
t
LZWE
WE HIGH to Low Z
[11]
10
ns
Notes:
10.Test conditions for all parameters other than tri-state parameters assume signal transition time of 3ns or less (1V/ns), timing reference levels of V
CC(typ.)
/2, input
pulse levels of 0 to V
, and output loading of the specified I
/I
OH
as shown in the “AC Test Loads and Waveforms” section.
11. At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
HZWE
is less than t
LZWE
for any given device.
12.t
, t
, and t
transitions are measured when the outputs enter a high impedance state.
13.The internal write time of the memory is defined by the overlap of WE, CE
= V
, and CE
= V
. All signals must be ACTIVE to initiate a write and any of these
signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write.
[+] Feedback
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| CY62168DV30LL-55BVXI | 功能描述:IC SRAM 16MBIT 55NS 48VFBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:MoBL® 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲器:RAM 存儲器類型:移動(dòng) SDRAM 存儲容量:256M（8Mx32） 速度:133MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.95 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應(yīng)商設(shè)備封裝:90-VFBGA（8x13） 包裝:帶卷 (TR) 其它名稱:557-1327-2 |
| CY62168DV30LL-55BVXIT | 功能描述:IC SRAM 16MBIT 55NS 48VFBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:MoBL® 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲器:RAM 存儲器類型:移動(dòng) SDRAM 存儲容量:256M（8Mx32） 速度:133MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.95 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應(yīng)商設(shè)備封裝:90-VFBGA（8x13） 包裝:帶卷 (TR) 其它名稱:557-1327-2 |
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