參數(shù)資料
型號(hào): CY62168DV30
廠(chǎng)商: Cypress Semiconductor Corp.
英文描述: 16-Mbit (2048K x 8) Static RAM
中文描述: 16兆位(2048K × 8)靜態(tài)RAM
文件頁(yè)數(shù): 1/9頁(yè)
文件大?。?/td> 231K
代理商: CY62168DV30
16-Mbit (2048K x 8) Static RAM
CY62168DV30
MoBL
Cypress Semiconductor Corporation
Document #: 38-05329 Rev. *D
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised September 14, 2004
Features
Very high speed: 55 ns and 70 ns
— Wide voltage range: 2.20V – 3.60V
Ultra-low active power
— Typical active current: 2 mA @ f = 1 MHz
— Typical active current: 15 mA @ f = f
max
Ultra-low standby power
Easy memory expansion with CE
1
, CE
2
and OE features
Automatic power-down when deselected
CMOS for optimum speed/power
Packages offered in a 48-ball FBGA
Functional Description
[1]
The CY62168DV30 is a high-performance CMOS static RAMs
organized as 2048Kbit words by 8 bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life
(MoBL
) in
portable applications such as cellular telephones. The device
also has an automatic power-down feature that significantly
reduces power consumption. The device can be put into
standby mode reducing power consumption by 90% when
addresses are not toggling. The device can be put into standby
mode reducing power consumption by more than 99% when
deselected Chip Enable 1 (CE
1
) HIGH or Chip Enable 2 (CE
2
)
LOW. The input/output pins (I/O
0
through I/O
7
) are placed in
a high-impedance state when: deselected Chip Enable 1
(CE
1
) HIGH or Chip Enable 2 (CE
2
) LOW, outputs are disabled
(OE HIGH), or during a write operation (Chip Enable 1 (CE
1
)
LOW and Chip Enable 2 (CE
2
) HIGH and WE LOW).
Writing to the device is accomplished by taking Chip Enable 1
(CE
1
) LOW and Chip Enable 2 (CE
2
) HIGH and Write Enable
(WE) input LOW. Data on the eight I/O pins (I/O
0
through I/O
7
)
is then written into the location specified on the address
pins(A
0
through A
20
).
Reading from the device is accomplished by taking Chip
Enable 1 (CE
1
) and Output Enable (OE) LOW and Chip
Enable 2 (CE
2
) HIGH while forcing Write Enable (WE) HIGH.
Under these conditions, the contents of the memory location
specified by the address pins will appear on the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
1
LOW and CE
2
HIGH), the outputs are disabled (OE HIGH), or
during a write operation (CE
1
LOW and CE
2
HIGH and WE
LOW). See the truth table for a complete description of read
and write modes.
Logic Block Diagram
Note:
1. For best practice recommendations, please refer to the Cypress application note entitled
System Design Guidelines
, available at http://www.cypress.com.
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
12
COLUMN
R
S
Data in Drivers
POWER
DOWN
WE
OE
I/O
0
I/O
1
I/O
2
I/O
3
2048K x 8
ARRAY
I/O
7
I/O
6
I/O
5
I/O
4
A
0
A
1
A
1
A
1
A
1
A
1
A
1
A
1
CE
1
CE
2
A
2
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