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參數(shù)資料
| 型號： | CY62157CV30LL-70BAE |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 512K x 16 Static RAM |
| 中文描述： | 512K X 16 STANDARD SRAM, 70 ns, PBGA48 |
| 封裝： | 6 X 10 MM, 1.20 MM HEIGHT, FBGA-48 |
| 文件頁數(shù)： | 6/13頁 |
| 文件大?。?/td> | 328K |
| 代理商： | CY62157CV30LL-70BAE |
CY62157CV30/33
Document #: 38-05014 Rev. *F
Page 6 of 13
Switching Characteristics
Over the Operating Range
[10]
Parameter
Description
70 ns
Unit
Min.
Max.
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE[11]
t
HZBE
Write Cycle
[14]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
BW
t
SD
t
HD
t
HZWE
t
LZWE
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE
1
LOW and CE
2
HIGH to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z
[11]
OE HIGH to High-Z
[11, 12]
CE
1
LOW and CE
2
HIGH to Low-Z
[11]
CE
1
HIGH or CE
2
LOW to High-Z
[11, 12]
CE
1
LOW and CE
2
HIGH to Power-up
CE
1
HIGH or CE
2
LOW to Power-down
BHE/BLE LOW to Data Valid
BHE/BLE LOW to Low-Z
[13]
BHE/BLE HIGH to High-Z
[11, 12]
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
70
10
70
35
5
25
10
25
0
70
70
5
25
Write Cycle Time
CE
1
LOW and CE
2
HIGH to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
BHE/BLE Pulse Width
Data Set-up to Write End
Data Hold from Write End
WE LOW to High-Z
[11, 12]
WE HIGH to Low-Z
[11]
70
60
60
0
0
50
60
30
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
25
5
Notes:
10.Test conditions assume signal transition time of 5 ns or less, timing reference levels of V
CC(typ.)
/2, input pulse levels of 0 to V
CC(typ.)
, and output loading of the
specified I
/I
and 30-pF load capacitance.
11. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZBE
is less than t
LZBE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any
given device.
12.t
, t
, t
, and t
transitions are measured when the outputs enter a high-impedance state.
13.When both byte enables are toggled together this value is 10 ns.
14.The internal Write time of the memory is defined by the overlap of WE, CE
= V
, BHE and/or BLE = V
, CE
= V
. All signals must be ACTIVE to initiate a
Write and any of these signals can terminate a Write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal
that terminates the Write.
[+] Feedback
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| CY62157CV30LL-70BAI | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 3V 8M-Bit 512K x 16 70ns 48-Pin FBGA 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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