參數(shù)資料
型號: CY62157CV30LL-70BAE
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 512K x 16 Static RAM
中文描述: 512K X 16 STANDARD SRAM, 70 ns, PBGA48
封裝: 6 X 10 MM, 1.20 MM HEIGHT, FBGA-48
文件頁數(shù): 2/13頁
文件大小: 328K
代理商: CY62157CV30LL-70BAE
CY62157CV30/33
Document #: 38-05014 Rev. *F
Page 2 of 13
Product Portfolio
Product
CY62157CV30
CY62157CV33
Range
Automotive-E
Automotive-A
Automotive-E
V
CC
Range
Typ.
[2]
3.0V
3.3V
Power Dissipation
Operating (I
CC
) mA
f = 1 MHz
Typ.
[2]
Max.
1.5
3
1.5
3
1.5
3
Standby (I
SB2
)
μ
A
Typ.
[2]
8
10
10
f = f
max
Min.
2.7V
3.0V
Max.
3.3V
3.6V
Typ.
[2]
7
5.5
7
Max.
15
12
15
Max.
70
30
80
Pin Configurations
[2, 3, 4]
FBGA (Top View)
3
Pin Definitions
Name
Definition
Input
A
0
-A
18
. Address Inputs
0
-I/O
15
. Data lines. Used as input or output lines depending on operation
WE
. Write Enable, Active LOW. When selected LOW, a WRITE is conducted. When selected HIGH, a READ is
conducted.
Input/Output
Input/Control
Input/Control
CE
1
. Chip Enable 1, Active LOW.
CE
2
. Chip Enable 2, Active HIGH.
OE
. Output Enable, Active LOW. Controls the direction of the I/O pins. When LOW, the I/O pins behave as
outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins
Input/Control
Input/Control
Ground
Vss
. Ground for the device
Power Supply
Vcc
. Power supply for the device
Notes:
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ.)
, T
A
= 25°C.
3. NC pins are not connected on the die.
4. E3 (DNU) can be left as NC or V
SS
to ensure proper application.
WE
A
11
A
10
A
6
A
0
A
3
CE
1
I/O
10
I/O
8
I/O
9
A
4
A
5
I/O
11
I/O
13
I/O
12
I/O
14
I/O
15
V
SS
A
9
A
8
OE
A
7
I/O
0
BHE
CE
2
A
17
A
2
A
1
BLE
V
CC
I/O
2
I/O
1
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
A
15
A
14
A
13
A
12
NC
A
18
NC
D
E
B
A
C
F
G
H
A
16
DNU
V
SS
V
CC
2
6
5
4
1
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