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參數(shù)資料
| 型號： | CY62157CV30LL-70BAE |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 512K x 16 Static RAM |
| 中文描述： | 512K X 16 STANDARD SRAM, 70 ns, PBGA48 |
| 封裝： | 6 X 10 MM, 1.20 MM HEIGHT, FBGA-48 |
| 文件頁數(shù)： | 5/13頁 |
| 文件大?。?/td> | 328K |
| 代理商： | CY62157CV30LL-70BAE |
CY62157CV30/33
Document #: 38-05014 Rev. *F
Page 5 of 13
Capacitance
[7]
Parameter
Description
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= V
CC(typ.)
Max.
6
8
Unit
pF
pF
C
IN
C
OUT
Input Capacitance
Output Capacitance
AC Test Loads and Waveforms
V
CC
Typ
V
CC
OUTPUT
R2
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
OUTPUT
V
TH
Equivalent to:
THéVENIN EQUIVALENT
ALL INPUT PULSES
R
TH
R1
Rise TIme: 1 V/ns
Fall Time: 1 V/ns
Parameters
R1
R2
R
TH
V
TH
3.0V
1.105
1.550
0.645
1.75
3.3V
1.216
1.374
0.645
1.75
Unit
Κ
Κ
Κ
V
Data Retention Characteristics
(Over the Operating Range)
Parameter
V
DR
I
CCDR
Description
Conditions
Min.
1.5
Typ.
[2]
Max.
Unit
V
μ
A
μ
A
V
CC
for Data Retention
Data Retention Current
V
CC
= 1.5V, CE
1
> V
CC
– 0.2V or
CE
2
< 0.2V,
V
IN
> V
CC
– 0.2V or V
IN
< 0.2V
Auto-A
4
4
20
60
Auto-E
t
CDR[8]
Chip Deselect to Data
Retention Time
Operation Recovery Time
0
ns
t
R[8]
t
RC
ns
Data Retention Waveform
[9]
Notes:
8. Full Device AC operation requires linear V
ramp from V
to V
> 100
μ
s or stable at V
>100
μ
s.
9. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
V
CC(min.)
t
R
V
CC(min.)
t
CDR
V
DR
> 1.5 V
DATA RETENTION MODE
CE
or
BHE.BLE
or
V
CC
CE
2
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| CY62157CV30LL-70BAI | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 3V 8M-Bit 512K x 16 70ns 48-Pin FBGA 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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