參數(shù)資料
型號(hào)： CY2833
廠商： Cypress Semiconductor Corp.
英文描述： Intel CK408 Mobile Clock Synthesizer
中文描述： 英特爾CK408移動(dòng)時(shí)鐘合成器
文件頁(yè)數(shù)： 4/18頁(yè)
文件大?。?/td> 224K
代理商： CY2833
CY28339
Document #: 38-07507 Rev. *A
Page 4 of 18
Byte 2:PCI Clock Control Register
(all bits are Read and Write functional)
Bi
t
7
6
5
4
3
2
1
0
@Pu
p
0
1
1
1
1
1
1
1
Nam
e
REF
PCI6
PCI5
PCI4
Description
REF Output Control. 0 = high strength, 1 = low strength.
PCI6 Output Control. 0 = forced LOW, 1 = enabled
PCI5 Output Control. 0 = forced LOW, 1 = enabled
PCI4 Output Control. 0 = forced LOW, 1 = enabled
Reserved
PCI2 Output Control. 0 = forced LOW, 1 = enabled
PCI1 Output Control. 0 = forced LOW, 1 = enabled
PCI0 Output Control. 0 = forced LOW, 1 = enabled
PCI2
PCI1
PCI0
Byte 3: PCIF Clock and 48M Control Register
(all bits are Read and Write functional)
Bit
@Pu
p
1
Name
Description
7
DOT_48
M
USB_48
M
PCIF
PCI8
PCI7
PCIF
PCI_8
PCI_7
DOT_48M Output Control. 0 = forced LOW, 1 = enabled
6
1
USB_48M Output Control. 0 = forced LOW,1 = enabled
5
4
3
2
1
0
0
1
1
1
1
1
PCI_STOP# Control of PCIF. 0 = Free Running, 1 = Stopped when PCI_STOP# is asserted.
PCI_STOP# Control of PCI8. 0 = Free Running, 1 = Stopped when PCI_STOP# is asserted.
PCI_STOP# Control of PCI7. 0 = Free Running, 1 = Stopped when PCI_STOP# is asserted.
PCIF Output Control. 0 = forced LOW, 1 = running
PCI_8 Output Control. 0 = forced LOW, 1 = running
PCI_7 Output Control. 0 = forced LOW, 1 = running
Byte 4: Control Register
(all bits are Read and Write functional)
Bit
7
6
5
4
3
2
1
0
@Pup
0
0
1
1
1
1
1
1
Name
Description
SS2 Spread Spectrum Control Bit. 0 = down spread, 1 = center spread).
Reserved. Set = 0.
3V66_0 Output Enable. 0 = disable, 1 = enabled
3V66_1/VCH Output Enable. 0 = disable, 1 = enabled
3V66_5 Output Enable. 0 = disable, 1 = enabled
66BUFF2/3V66_4 Output Enable. 0 = disable, 1 = enabled
66BUFF1/3V66_3 Output Enable. 0 = disable, 1 = enabled
66BUFF0/3V66_2 Output Enable. 0 = disable, 1 = enabled
3V66_0
3V66_1/VCH
3V66_5
19
18
66BUFF0/3V66_2
Byte 5:Clock Control Register
(all bits are Read and Write functional)
Bit
7
6
5
4
3
2
@Pup
0
1
0
0
0
0
Name
Description
SS1 Spread Spectrum Control Bit.
SS0 Spread Spectrum Control Bit.
66IN to 66M delay Control MSB.
66IN to 66M delay Control LSB.
Reserved. Set = 0.
DOT_48M Edge Rate Control. When set to 1, the edge is slowed by
15%.
Reserved. Set = 0.
USB_48M edge rate control. When set to 1, the edge is slowed by 15%.
DOT_48M
1
0
0
0
USB_48M
相關(guān)PDF資料
PDF描述
CY28339ZCXT Intel CK408 Mobile Clock Synthesizer
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY28330 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Clock Generator for AMD⑩ Hammer
CY28330OC 制造商:Cypress Semiconductor 功能描述:
CY28330OCT 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Clock Generator for AMD⑩ Hammer
CY28331 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Clock Generator for AMD⑩ Hammer
CY28331-2 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Clocks and Buffers
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