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參數(shù)資料
| 型號： | CY2833 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Intel CK408 Mobile Clock Synthesizer |
| 中文描述： | 英特爾CK408移動時鐘合成器 |
| 文件頁數(shù)： | 2/18頁 |
| 文件大?。?/td> | 224K |
| 代理商： | CY2833 |
CY28339
Document #: 38-07507 Rev. *A
Page 2 of 18
Pin Definitions
Pin Number
47
1
2
43, 42,
39, 38
29
31
20
Name
I/O
Description
REF0
XIN
XOUT
CPUT1,CPUC1
CPUT2, CPUC2
3V66_0
3V66_1/VCH
66IN/3V66_5
3.3V 14.318-MHz clock output
.
14.318-MHz crystal input
.
14.318-MHz crystal input
.
Differential CPU clock outputs
.
3.3V 66-MHz clock output
.
3.3V selectable through SMBus to be 66 MHz or 48 MHz
.
66-MHz input to buffered 66BUFF and PCI or 66-MHz clock from internal
VCO
.
66-MHz buffered outputs from 66Input or 66-MHz clocks from internal VCO
.
17, 18, 19
66BUFF [2:0]
/3V66 [4:2]
PCIF
6
33 MHz clocks divided down from 66Input or divided down from 3V66
; PCIF
default is free-running.
PCI clock outputs divided down from 66Input or divided down from 3V66
;
PCI [7:8] are configurable as free-running PCI through SMBus.
[2]
8, 9, 10, 12, 13,
14, 4, 5
PCI [0:2]
PCI [4:6]
PCI [7:8]
USB_48M
DOT_48M
S2
S1
IREF
35
34
36
46
37
Fixed 48-MHz clock output
.
Fixed 48-MHz clock output
.
Special 3.3V three-level input for Mode selection
.
3.3V LVTTL inputs for CPU frequency selection
.
A precision resistor is attached to this pin which is connected to the
internal current reference
.
3.3V LVTTL input for Power_Down# (active LOW)
.
3.3V LVTTL input for PCI_STOP# (active LOW)
.
3.3V LVTTL input for CPU_STOP# (active LOW)
.
3.3V LVTTL input is a level-sensitive strobe used to determine when S[2:1]
inputs are valid and OK to be sampled (Active LOW)
. Once VTT_PWRGD#
is sampled LOW, the status of this input will be ignored.
SMBus-compatible SDATA
.
SMBus-compatible SCLK
.
3.3V power supply for outputs
.
21
30
45
24
PD#
PCI_STOP#
CPU_STOP#
VTT_PWRGD#
25
26
11, 15, 28, 40, 44,
48
SDATA
SCLK
VDD_PCI,
VDD_3V66,
VDD_CPU,VDD_RE
F
VDD_48 MHz
VDD_CORE
GND_REF,
GND_PCI,
GND_3V66,
GND_IREF,
GND_CPU
GND_CORE
33
22
3, 7, 16, 27, 32,
41
3.3V power supply for 48 MHz
.
3.3V power supply for phase-locked loop (PLL)
.
Ground for outputs
.
23
Ground for PLL
.
Note:
2.
PCI3 is internally disabled and is not accessible.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY28330 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Clock Generator for AMD⑩ Hammer |
| CY28330OC | 制造商:Cypress Semiconductor 功能描述: |
| CY28330OCT | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Clock Generator for AMD⑩ Hammer |
| CY28331 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Clock Generator for AMD⑩ Hammer |
| CY28331-2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Clocks and Buffers |
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