
CY28339
Document #: 38-07507 Rev. *A
Page 15 of 18
Test and Measurement Set-up
For Differential CPU Output Signals
The following diagram shows lumped test load configurations
for the differential Host Clock Outputs.
T
CCJ
PCIF and PCI Cycle to
Cycle Jitter
Measurement at 1.5V
–
250
ps
DOT_48M
T
DC
T
PERIOD
T
R
/ T
F
T
CCJ
DOT_48M
Duty Cycle
DOT_48M Period
DOT_48M Rise and Fall Times
DOT_48M Cycle to Cycle Jitter
Measurement at 1.5V
Measurement at 1.5V
Measured between 0.4V and 2.4V
Measurement at 1.5V
USB_48M
Measurement at 1.5V
Measurement at 1.5V
Measured between 0.4V and 2.4V
Measurement at 1.5V
45
55
%
ns
ns
ps
20.83
0.5
–
20.83
1.0
350
T
DC
T
PERIOD
T
R
/ T
F
T
CCJ
USB_48M Duty Cycle
USB_48M Period
USB_48M Rise and Fall Times
DOT_48M Cycle to Cycle Jitter
45
55
%
ns
ns
20.82
1.0
20.83
2.0
–
350
ps
REF
T
DC
T
PERIOD
T
R
/ T
F
T
CCJ
REF Duty Cycle
REF Period
REF Rise and Fall Times
REF Cycle to Cycle Jitter
Measurement at 1.5V
Measurement at 1.5V
Measured between 0.4V and 2.4V
Measurement at 1.5V
ENABLE/DISABLE and SETUP
When XIN is driven from external clock source
45
55
%
ns
V/ns
ps
69.827 69.855
1.0
–
4.0
1000
T
PZL
/T
PZH
T
PZL
/T
PZH
T
STABLE
T
SS
T
SH
Output Enable Delay (All Outputs)
Output Disable Delay (All Outputs)
Clock Stabilization from Power-up
Stopclock Set Up Time
Stopclock Hold Time
1.0
1.0
–
10.0
10.0
10.0
3.0
–
ns
ns
ms
ns
CPU_STOP# and PIC_STOP# set up time with
respect to PCIF clock to guarantee that the
effected clock will stop or start at the next PCIF
clock’s rising edge.
When crystal meets min. 40
device series resis-
tance specification
0
–
ns
T
SU
Oscillator Start-up time
AC Electrical Specifications
(continued)
Parameter
Description
Condition
Min.
Max.
Unit
Measurement Point
2pF
CPUT
T
PCB
T
PCB
CPUC
330
63.4
63.4
475
33.2
33.2
Measurement Point
2pF
Figure 15. 1.0V Test Load Termination