參數(shù)資料
型號(hào): CXD3009Q
廠商: Sony Corporation
元件分類: 數(shù)字信號(hào)處理
英文描述: CD Digital Signal Processor(CD數(shù)字信號(hào)處理器)
中文描述: CD數(shù)字信號(hào)處理器(光盤數(shù)字信號(hào)處理器)
文件頁(yè)數(shù): 56/64頁(yè)
文件大?。?/td> 477K
代理商: CXD3009Q
56
CXD3009Q
5. 1bit DAC Block
5-1. DAC Block Input Timing
Timing Chart 5-1 shows the input timing for the DAC block.
The data from the CD signal processor block to the DAC block can be connected inside the IC by setting the
OUTL command of $8X to 1. Set OUTL1 to 0 when the data is send to the DAC block via the audio DSP and
the like.
5-2. Description of DAC Block Functions
Zero data detection
When the condition where the lower 4bits of the input data are DC and the remaining upper bits are all "0" or
all "1" has continued for approximately 300ms, zero data is detected. Zero data detection is performed
independently for the left and right channels.
Mute flag output
The LMUT and RMUT pins go active when any one of the following conditions is met.
The polarity can be selected by the ZDPL command of $9X.
When zero data is detected
When a high signal is input to the SYSM pin
When the SMUT command of $AX is set
Attenuation operation
Assuming attenuation data X1, X2 and X3 (X1 > X3 > X2), the corresponding audio outputs are Y1, Y2 and
Y3 (Y1 > Y3 > Y2). First, X1 is sent, followed by X2. If X2 is sent before X1 reaches Y1 (A in the figure), X1
continues approaching Y2. Next, if X3 is sent before X1 reaches Y2 (B or C in the figure), X1 then
approaches Y3 from the value (B or C in the figure) at that point.
A
Y1
B
Y3
C
Y2
23.2 [ms]
00 (H)
0dB
7F (H)
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