參數(shù)資料
型號: CXD3009Q
廠商: Sony Corporation
元件分類: 數(shù)字信號處理
英文描述: CD Digital Signal Processor(CD數(shù)字信號處理器)
中文描述: CD數(shù)字信號處理器(光盤數(shù)字信號處理器)
文件頁數(shù): 25/64頁
文件大小: 477K
代理商: CXD3009Q
25
CXD3009Q
Signal
PER0 to 7
FOK
GFS
LOCK
EMPH
ALOCK
VF0 to 7
SPOA, B
WFCK
SCOR
GTOP
RFCK
XRAOF
L0 to L7,
R0 to R7
RF jitter amount (used to adjust the focus bias). 8-bit binary data in PER0 = LSB, PER7 = MSB.
Focus OK
High when the frame sync and the insertion protection timing match.
GFS is sampled at 460Hz; when GFS is high, a high signal is output. If GFS is low eight
consecutive samples, a low signal is output.
High when the playback disc has emphasis.
GFS is sampled at 460Hz; when GFS is high eight consecutive samples, a high signal is
output. If GFS is low eight consecutive samples, a low signal is output.
Used in CAV-W mode. Results of measuring the disc rotational velocity. (See Timing Chart 2-3.)
VF0 = LSB, VF7 = MSB.
SPOA and B pin inputs.
Write frame clock output.
High when either subcode sync S0 or S1 is detected.
High when the sync protection window is open.
Read frame clock output.
Low when the built-in 16K RAM exceeds the ±4 frame jitter margin.
Peak meter register output. L0 to 7 are the left-channel and R0 to 7 are the right-channel peak
data. L0 and R0 are LSB.
Description
C1F1
0
1
1
0
0
1
No Error
Single Error Correction
Irretrievable Error
C1F2
C1 correction status
C2F1
0
1
1
0
0
1
No Error
Single Error Correction
Irretrievable Error
C2F2
C2 correction status
Command bit
CPUSR = 1
CPUSR = 0
XLON pin is high.
XLON pin is low.
Processing
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