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參數(shù)資料
| 型號： | CXD3009Q |
| 廠商： | Sony Corporation |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | CD Digital Signal Processor(CD數(shù)字信號處理器) |
| 中文描述： | CD數(shù)字信號處理器（光盤數(shù)字信號處理器） |
| 文件頁數(shù)： | 34/64頁 |
| 文件大小： | 477K |
| 代理商： | CXD3009Q |
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CXD3009Q
1-2. Description of SENS Output
The following signals are output from SENS, depending on the microcomputer serial register value (latching
not required).
Note that the SENS output can be read out from the SQSO pin when SOCT = 0, SL1 = 1 and SL0 = 0.
(See the $BX commands.)
2. Subcode Interface
This section explains the subcode interface.
There are two methods for reading out a subcode externally.
The 8-bit subcodes P to W can be read from SBSO by inputting EXCK to the CXD3009Q.
Sub Q can be read out after checking the CRC of the 80bits in the subcode frame.
Sub Q can be read out from the SQSO pin by inputting 80 clock pulses to the SQCK pin when SCOR comes
correctly and CRCF is high.
2-1. P to W Subcode Readout
Data can be read out by inputting EXCK immediately after WFCK falls. (See Timing Chart 2-1.)
2-2. 80-bit Sub Q Readout
Fig. 2-1 shows the peripheral block of the 80-bit Sub Q register.
First, Sub Q, regenerated at one bit per frame, is input to the 80-bit serial/parallel register and the CRC
check circuit.
96-bit Sub Q is input, and if the CRC is OK, it is output to SQSO with CRCF = 1. In addition, 80bits are
loaded into the parallel/serial register.
When SQSO goes high 400μs (monostable multivibrator time constant) or more after subcode readout, the
CPU determines that new data (which passed the CRC check) has been loaded.
When the 80-bit data is loaded, the order of the MSB and LSB is inverted within each byte. As a result,
although the sequence of bytes is the same, the bits within the bytes are now ordered LSB first.
Once the 80-bit data load is confirmed, SQCK is input so that the data can be read.
The SQCK input is detected, and the retriggerable monostable multivibrator is reset while the input is low.
The retriggerable monostable multivibrator has a time constant from 270μs to 400μs. When the duration
when SQCK is high is less than this time constant, the monostable multivibrator is kept reset; during this
interval, the serial/parallel register is not loaded into the parallel/serial register.
While the monostable multivibrator is being reset, data cannot be loaded in the 80-bit parallel/serial register.
In other words, while reading out with a clock cycle shorter than this time constant, the register will not be
rewritten by CRCOK and others. (See Timing Chart 2-2.)
The high and low intervals for SQCK should be between 750ns and 120μs.
SEIN, a signal input to this LSI from the SSP, is output.
Low while the auto sequencer is in operation, high when operation
terminates.
Outputs the signal input to the FOK pin. Normally, FOK (from RF) is
input. High for "focus OK".
SEIN, a signal input to this LSI from the SSP, is output.
High when the regenerated frame sync is obtained with the correct timing.
Low when the EFM signal, after passing through the sync detection
filter, is lengthened by 64 channel clock pulses or more.
SENS pin is fixed to low.
Calculates the number of tracks from the frequency division ratio set
by $B.High when $C is latched; toggles each time CNIN is input the
number of times set in register B.
SEIN
XBUSY
FOK
SEIN
GFS
OV64
“
L
”
CNIN
division
$0X, 1X, 2X, 3X
$4X
$5X
$6X
$AX
$EX
$7X, 8X, 9X, BX, DX, FX
$CX
Microcomputer serial
register value
(latching not required)
SENS
output
Meaning
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CXD3011R-1 | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:CD Digital Signal Processor with Built-in Digital Servo and DAC |
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| CXD3018Q/R | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CD Digital Signal Processor with Built-in DigitalServo and DAC |
| CXD3021 | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:CD Digital Signal Processor with Built-in Digital Servo and DAC |
| CXD3021R | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:CD Digital Signal Processor with Built-in Digital Servo and DAC |
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