參數(shù)資料
型號: CS5460A-BS
廠商: CIRRUS LOGIC INC
元件分類: ADC
英文描述: Single Phase Bi-Directional Power/Energy IC
中文描述: 2-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO24
封裝: MO-150, SSOP-24
文件頁數(shù): 44/54頁
文件大小: 876K
代理商: CS5460A-BS
CS5460A
44
5. REGISTER DESCRIPTION
Note: 1.
** “default” => bit status after software or hardware reset
Note that all registers can be read from, and written to.
2.
5.1 Configuration Register
Address: 0
Default** = 0x000001
K[3:0]
Clock divider. A 4 bit binary number used to divide the value of MCLK to generate the internal
clock DCLK. The internal clock frequency is DCLK = MCLK/K. The value of K can range be-
tween 1 and 16. Note that a value of “0000” will set K to 16 (not zero).
iCPU
Inverts the CPUCLK clock. In order to reduce the level of noise present when analog signals
are sampled, the logic driven by CPUCLK should not be active during the sample edge.
0 = normal operation (default)
1 = minimize noise when CPUCLK is driving rising edge logic
IHPF
Control the use of the High Pass Filter on the Current Channel.
0 = High-pass filter is disabled. If VHPF is set, use all-pass filter. Otherwise, no filter is used.
(default)
1 = High-pass filter is enabled.
VHPF
Control the use of the High Pass Filter on the voltage Channel.
0 = High-pass filter is disabled. If IHPF is set, use all-pass filter. Otherwise, no filter is used.
(default)
1 = High-pass filter enabled
23
PC6
22
PC5
21
PC4
20
PC3
19
PC2
18
PC1
17
PC0
16
Gi
15
14
Res
13
Res
12
SI1
11
SI0
10
EOD
9
8
EWA
DL1
DL0
7
6
5
4
3
2
1
0
RS
VHPF
IHPF
iCPU
K3
K2
K1
K0
Current
Channel
Voltage
Channel
Cycle-Counter Registe
Status Register (1 × 24)
Serial Interface
Mask Register (1 × 24)
Unsigned Output Registers (2 × 24)
(I
, V
)
RMS
RMS
Command Word
State Machine
Transmit Buffer
Receive Buffer
Signed Output Registers (4 × 24)
(I, V, P, E)
24-Bit
SDI
CS
SDO
SCLK
INT
AC Offset Register (1 x 24)
AC Offset Register (1 x 24)
Control Register (1 x 24)
Power Offset Register (1 x 24)
Configuration Register (1 × 24)
Pulse-Rate Register (1 × 24)
Offset Register (1 × 24)
DC
Offset Register (1 × 24)
DC
Gain Register (1 × 24)
AC/DC
Gain Register (1 × 24)
AC/DC
r (1 × 24)
Timebase Cal. Register (1 x 24)
Figure 21. CS5460A Register Diagram
相關(guān)PDF資料
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