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參數(shù)資料
| 型號(hào)： | CS5460A-BS |
| 廠商： | CIRRUS LOGIC INC |
| 元件分類： | ADC |
| 英文描述： | Single Phase Bi-Directional Power/Energy IC |
| 中文描述： | 2-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO24 |
| 封裝： | MO-150, SSOP-24 |
| 文件頁數(shù)： | 12/54頁 |
| 文件大?。?/td> | 876K |
| 代理商： | CS5460A-BS |
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CS5460A
12
2. GENERAL DESCRIPTION
The CS5460A is a CMOS monolithic power mea-
tation engine. The CS5460A combines two
programmable gain amplifiers, two
Σ
modulators,
two high rate filters, system calibration, and
rms/power calculation functions to provide instan-
taneous voltage/current/power data samples as
well as periodic computation results for real (bill-
able) energy, V
RMS
, and I
RMS
. In order to accom-
modate lower cost metering applications, the
CS5460A can also generate pulse-train signals on
certain output pins, for which the number of pulses
emitted on the pins is proportional to the quantity of
real (billable) energy registered by the device.
The CS5460A is optimized for power measure-
ment applications and is designed to interface to a
shunt or current transformer to measure current,
and to a resistive divider or potential transformer to
measure voltage. To accommodate various input
voltage levels, the current channel includes a pro-
grammable gain amplifier (PGA) which provides
two full-scale input levels, while the voltage chan-
nel’s PGA provides a single input voltage range.
With a single +5 V supply on VA+/-, both of the
CS5460A’s input channels can accomodate com-
mon mode + signal levels between -0.25 V and
VA+.
The CS5460A includes two high-rate digital filters
(one per channel), which decimate/integrate the
output from the 2
Σ
modulators. The filters yield
24-bit output data at a (MCLK/K)/1024 output word
rate (OWR). The OWR can be thought of as the ef-
fective sample frequency of the voltage channel and
the current channel.
To facilitate communication to a microcontroller,
the CS5460A includes a simple three-wire serial
interface which is SPI and Microwire compati-
ble. The serial port has a Schmitt Trigger input on
its SCLK (serial clock) and RESET pins to allow for
slow rise time signals.
2.1 Theory of Operation
A computational flow diagram for the two data
paths is shown in Fig. 3. The reader should refer to
this diagram while reading the following data pro-
cessing
description,
block-by-block.
which
is
covered
2.1.1
Σ
Modulators
The analog waveforms at the voltage/current chan-
nel inputs are subject to the gains of the input
PGAs (not shown in Figure 3). These waveforms
are then sampled by the delta-sigma modulators at
a rate of (MCLK/K)/8 Sps.
2.1.2 High-Rate Digital Low-Pass Filters
The data is then low-pass filtered, to remove
high-frequency noise from the modulator output.
Referring to Figure 3, the high rate filter on the volt-
age channel is implemented as a fixed Sinc
2
filter.
The current channel uses a Sinc
4
filter, which al-
lows the current channel to make accurate mea-
surements over a wider span of the total input
range, in comparison to the accuracy range of the
voltage channel. (This subject is discussed more in
Section 2.2.1)
Also note from Figure 3 that the digital data on the
voltage channel is subjected to a variable time-de-
lay filter. The amount of delay depends on the val-
ue of the seven phase compensation bits (see
Phase Compensation). Note that when the phase
compensation bits PC[6:0] are set to their default
setting of “0000000” (and if MCLK/K = 4.096 MHz)
then the nominal time delay that is imposed on the
original analog voltage input signal, with respect to
the original analog current input signal, is ~1.0
μ
s.
This translates into a delay of ~0.0216 degrees at
60 Hz.
2.1.3 Digital Compensation Filters
The data from both channels is then passed
through two FIR compensation filters, whose pur-
pose is to compensate for the magnitude roll-off of
the low-pass filtering operation (mentioned earli-
er).
2.1.4 Digital High-Pass Filters
Both channels provide an optional high-pass filter
(denoted as “HPF” in Figure 3) which can be en-
gaged into the signal path, to remove the DC con-
tent from the current/voltage signal before the
RMS/energy calculations are made. These filters
are activated by enabling certain bits in the Config-
uration Register.
If e high-pass filter is engaged in only one of the
two channels, then the all-pass filter (see “APF” in
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CS5460A | Single Phase Bi-Directional Power/Energy IC |
| CS5460 | Single Phase Bi-Directional Power/Energy IC(單相雙向功率/能量IC) |
| CS5461A-IS | Single Phase, Bi-directional Power/Energy IC |
| CS5461A-ISZ | Single Phase, Bi-directional Power/Energy IC |
| CS5461A | Single Phase, Bi-directional Power/Energy IC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CS5460A-BSZ | 功能描述:電流和電力監(jiān)控器、調(diào)節(jié)器 Single-Phase Bi-Dir Power/Energy IC RoHS:否 制造商:STMicroelectronics 產(chǎn)品:Current Regulators 電源電壓-最大:48 V 電源電壓-最小:5.5 V 工作溫度范圍:- 40 C to + 150 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:HPSO-8 封裝:Reel |
| CS5460A-BSZ | 制造商:Cirrus Logic 功能描述:Driver IC 制造商:Cirrus Logic 功能描述:IC ENERGY METERING 1PHASE 24SSOP 制造商:Cirrus Logic 功能描述:IC, ENERGY METERING, 1PHASE, 24SSOP |
| CS5460A-BSZR | 功能描述:電流和電力監(jiān)控器、調(diào)節(jié)器 IC Sngl-Phs BiDirect PWR/Energy RoHS:否 制造商:STMicroelectronics 產(chǎn)品:Current Regulators 電源電壓-最大:48 V 電源電壓-最小:5.5 V 工作溫度范圍:- 40 C to + 150 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:HPSO-8 封裝:Reel |
| CS5460-BS | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Cirrus Logic 功能描述: |
| CS5460C-ISZ | 功能描述:電流和電力監(jiān)控器、調(diào)節(jié)器 Sngl-Phs Bi-Drctnl Power/Energy RoHS:否 制造商:STMicroelectronics 產(chǎn)品:Current Regulators 電源電壓-最大:48 V 電源電壓-最小:5.5 V 工作溫度范圍:- 40 C to + 150 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:HPSO-8 封裝:Reel |
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