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參數(shù)資料
| 型號： | C9827JY |
| 英文描述： | Up to 5A ULDO linear regulator |
| 中文描述： | CPU系統(tǒng)時(shí)鐘發(fā)生器| SSOP封裝| 56PIN |塑料 |
| 文件頁數(shù)： | 20/25頁 |
| 文件大?。?/td> | 170K |
| 代理商： | C9827JY |
C9827J
High Performance Pentium 4 Clock Synthesizer
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07107 Rev. **
5/24/2001
Page 20 of 25
PD# - De-assertion (transition from logic ‘0’ to logic ‘1’)
The power-up latency between PD# rising to a valid logic ‘1’ level and the starting of all clocks is less than 3.0 mS.
CPU 133MHz
CPU# 133MHz
3V66
66In
REF 14.318MHz
USB 48MHz
PCIF / APIC
33MHz
PCI 33MHz
66Buff[0,2]
PWRDWN#
66Buff1 / GMCH
100uS max
<3mS
30uS min
Power Down De-Assertion Timing Waveforms Figure
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