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| 型號(hào)： | C9827JY |
| 英文描述： | Up to 5A ULDO linear regulator |
| 中文描述： | CPU系統(tǒng)時(shí)鐘發(fā)生器| SSOP封裝| 56PIN |塑料 |
| 文件頁數(shù)： | 11/25頁 |
| 文件大小： | 170K |
| 代理商： | C9827JY |
C9827J
High Performance Pentium 4 Clock Synthesizer
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07107 Rev. **
5/24/2001
Page 11 of 25
Test and Measurement Setup (Cont.)
For single Ended Output Signals
Figure 2
Buffer Characteristics
Current Mode CPU Clock Buffer Characteristics
The current mode output buffer detail and current reference circuit details are contained in the previous table of this data
sheet. The following parameters are used to specify output buffer characteristics:
1. Output impedance of the current mode buffer circuit - Ro (see figure below).
2. Minimum and maximum required voltage operation range of the circuit – Vop (see figure below).
3. Series resistance in the buffer circuit – Ros (see figure below).
4. Current accuracy at given configuration into nominal test load for given configuration.
2.4V
0.4V
3.3V
0V
Tr
Tf
1.5V
3.3V signals
tDC
Probe
Output under Test
Load Cap
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