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參數(shù)資料
| 型號： | C9827JY |
| 英文描述： | Up to 5A ULDO linear regulator |
| 中文描述： | CPU系統(tǒng)時鐘發(fā)生器| SSOP封裝| 56PIN |塑料 |
| 文件頁數(shù)： | 18/25頁 |
| 文件大?。?/td> | 170K |
| 代理商： | C9827JY |
C9827J
High Performance Pentium 4 Clock Synthesizer
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07107 Rev. **
5/24/2001
Page 18 of 25
PD# (Power Down) Clarification
The PD# (Power Down) pin is used to shut off ALL clocks prior to shutting off power to the device. PD# is an
asynchronous active low input. This signal is synchronized internally to the device powering down the clock synthesizer.
PD# is an asynchronous function for powering up the system. When PD# is low, all clocks are driven to a low value and
held there and the VCO and PLL’s are also powered down. All clocks are shut down in a synchronous manner so has
not to cause glitches while transitioning to the low ‘stopped’ state.
PD# Functionality
PD#
1
0
CPU
Normal
Iref*2
CPU#
Normal
Float Low
DRCG
66M
Low
66CLK (0:2)
66Input
Low
PCI_F/PCI
66Input/2
Low
PCI
USB/DOT
48M
Low
66Input/2
Low
PD# - Assertion (transition from logic ’l’ to logic ‘0’)- Buffered Mode
When PD# is sampled low by two consecutive rising edges of the CPU# clock, then on the next high to low transition of
PCIF, the PCIF clock is stopped low. On the next high to low transition of 66Buff, the 66Buff clock is stopped low. From
this time, each clock will stop low on it’s next high to low transition, except the CPU clock. The CPU clocks are held with
the CPU clock pin driven high with a value of 2 x Iref, and CPU# un-driven. After the last clock has stopped, the rest of
the generator will be shut down.
66Buff[0..2]
PCIF
PWRDWN#
CPU 133MHz
CPU# 133MHz
3V66
66In
REF 14.318MHz
USB 48MHz
Power Down Assertion Timing Waveforms Figure – Buffered Mode
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