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參數(shù)資料
| 型號： | C9827JY |
| 英文描述： | Up to 5A ULDO linear regulator |
| 中文描述： | CPU系統(tǒng)時鐘發(fā)生器| SSOP封裝| 56PIN |塑料 |
| 文件頁數(shù)： | 14/25頁 |
| 文件大?。?/td> | 170K |
| 代理商： | C9827JY |
C9827J
High Performance Pentium 4 Clock Synthesizer
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07107 Rev. **
5/24/2001
Page 14 of 25
66BUF to PCI Buffered Clock Skew
The following figure shows the difference (skew) between the 3V33(0:5) outputs when the 66M clocks are connected to
66IN. This offset is described in the Group Timing Relationship and Tolerances section of this data sheet. The
measurements were taken at 1.5 volts.
66BUF(0:2)
PCI(0:6)
PCIF(0:2)
1.5-
3.5ns
Buffer Mode – 33V66(0:1); 66BUF(0:2) Phase Relationship
3V66 to PCI Un-Buffered Clock Skew
The following figure show the timing relationship between 3V66_(0:5) and PCI(0:6) and PCIF(0:2) when configured to
run in the un-buffered mode.
3V66_(0:5)
PCI(0:6)
PCIF(0:2)
1.5-
3.5ns
Un-buffered Mode - 3V66_(0:5) to PCI (0:6) and PCIF(0:2) Phase Relationship
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